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quad parametric measurement unit with integrated 16-bit level setting dacs ad5522 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2011 analog devices, inc. all rights reserved. features quad parametric measurement unit (pmu) fv, fi, fn (high-z), mv, mi functions 4 programmable current ranges (internal r sense ) 5 a, 20 a, 200 a, and 2 ma 1 programmable current range up to 80 ma (external r sense ) 22.5 v fv range with asymmetrical operation integrated 16-bit dacs provide programmable levels gain and offset correction on chip low capacitance outputs suited to relayless systems on-chip comparators per channel fi voltage clamps and fv current clamps guard drive amplifier system pmu connections programmable temperature shutdown spi- and lvds-compatible interfaces compact 80-lead tqfp with exposed pad (top or bottom) applications automated test equipment (ate) per-pin parametric measurement unit continuity and leakage testing device power supply instrumentation source measure unit (smu) precision measurement functional block diagram 16 16 16 dutgnd measvh[0:3] guard[0:3] cgalm sclk sync sdi sdo cpol0/ sclk cpol2/ cpo0 cpoh2/ cpo1 cpol3/ cpo2 cpoh3/ cpo3 serial interface cpoh0/ sdi cpol1/ sync cpoh1/ sdo spi/ lvds reset busy 16 clamp and guard alarm temp sensor power-on reset guardin[0:3]/ dutgnd[0:3] dut externa l r sense (currents up to 80ma) extmeasih[0:3] extmeasil[0:3] foh[0:3] extfoh[0:3] cff[0:3] fin clh cll avss avdd agnd + ? measout[0:3] 4 dgnd cph comparator ccomp[0:3] load cpl internal range select (5a, 20a, 200a, 2ma) ? ? ? ? + + ? + ? + + + r sense ? ? + + 16 16 16 16 16 vref sys_force sys_sense dvcc 16 x1 reg c reg m reg 16 16 16 16 16 16 16 16-bit fin dac 5 or 10 2 1 tmpalm agnd refgnd 16-bit clh dac measout mux and gain 1/0.2 x1 reg c reg m reg x1 reg c reg m reg 16 2 16 16 16 16 x1 reg c reg m reg 6 6 offset dac 16-bit offset dac to all dac output amplifiers force amplifier 16-bit cll dac 16-bit cph dac 16-bit cpl dac sw1 sw2 sw3 sw4 60? sw6 sw5 sw9 sw8 sw10 sw11 measure voltage in-amp measure current in-amp temp sensor to measout mux sw12 x1 reg c reg m reg 6 x2 reg x2 reg x2 reg 6 x2 reg x2 reg 6 6 2 2 agnd en 1k? guard amp sw13 sw14 agnd 10k ? sw15 sw16 dutgnd vmid to center i range + ? 06197-001 agnd sw7 4k ? 2k ? measvh (hi-z) 4k ? figure 1.
ad5522 rev. d | page 2 of 64 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 general description ......................................................................... 4 specifications..................................................................................... 6 timing characteristics .............................................................. 11 absolute maximum ratings.......................................................... 15 thermal resistance .................................................................... 15 esd caution................................................................................ 15 pin configurations and function descriptions ......................... 16 typical performance characteristics ........................................... 22 terminology .................................................................................... 29 theory of operation ...................................................................... 30 force amplifier........................................................................... 30 comparators................................................................................ 30 clamps ......................................................................................... 30 current range selection............................................................ 31 high current ranges ................................................................. 31 measure current gains.............................................................. 32 vmid voltage............................................................................. 32 choosing power supply rails ................................................... 33 measure output (measoutx pins) ...................................... 33 device under test ground (dutgnd)................................. 33 guard amplifier ......................................................................... 34 compensation capacitors ......................................................... 34 system force and sense switches............................................. 35 temperature sensor ................................................................... 35 dac levels ...................................................................................... 36 offset dac .................................................................................. 36 gain and offset registers.......................................................... 36 cached x2 registers................................................................... 37 reference voltage (vref)......................................................... 37 reference selection .................................................................... 37 calibration................................................................................... 38 additional calibration............................................................... 39 system level calibration........................................................... 39 circuit operation ........................................................................... 40 force voltage (fv) mode .......................................................... 40 force current (fi) mode........................................................... 41 serial interface ................................................................................ 42 spi interface ................................................................................ 42 lvds interface............................................................................ 42 serial interface write mode...................................................... 42 reset function ......................................................................... 42 busy and load functions ..................................................... 42 register update rates ................................................................ 44 register selection ....................................................................... 44 write system control register ................................................. 46 write pmu register................................................................... 48 write dac register ................................................................... 50 read registers............................................................................. 53 readback of system control register...................................... 54 readback of pmu register ....................................................... 55 readback of comparator status register................................ 56 readback of alarm status register.......................................... 56 readback of dac register........................................................ 57 applications information .............................................................. 58 power-on default ...................................................................... 58 setting up the device on power-on ....................................... 58 changing modes ........................................................................ 59 required external components............................................... 59 power supply decoupling ......................................................... 60 power supply sequencing ......................................................... 60 typical application for the ad5522........................................ 60 outline dimensions ....................................................................... 62 ordering guide .......................................................................... 63
ad5522 rev. d | page 3 of 64 revision history 2/11rev. c to rev. d changes to measure current, gain error tempco parameter....6 changes to force current, common mode error (gain = 5) and common mode error (gain = 10) parameters .....................7 changes to figure 5.........................................................................13 changes to figure 6.........................................................................14 changes to figure 15 ......................................................................22 changes to high current ranges section ...................................31 changes to gain and offset registers section ............................36 changes to endnote 1 in table 17 and figure 56........................43 changes to register update rates and figure 57 .......................44 changes to bit 15 to bit 0 description in table 28 .....................50 5/10rev. b to rev. c changes to compensation capacitors section ...........................34 changes to gain and offset registers section ............................36 changes to table 14 and reducing zero-scale error section ..38 changes to serial interface write mode section and busy and load functions section ...............................................................42 changes to table 17 ........................................................................43 added table 18; renumbered sequentially.................................43 changes to register update rates section ..................................44 changes to table 23 ........................................................................46 changes to table 31 ........................................................................54 10/09rev. a to rev. b changes to table 1 ............................................................................6 changes to table 2 ..........................................................................11 added figure 13 and figure 15; renumbered sequentially ......22 added figure 16 ..............................................................................23 changes to figure 21 ......................................................................23 changes to clamps section ...........................................................30 changes to table 22, bit 21 to bit 18 description ......................44 changes to table 25, bit 9 description ........................................47 changes to table 28 ........................................................................49 changes to figure 59 ......................................................................59 10/08rev. 0 to rev. a changes to table 1 ............................................................................6 change to 4 dac x1 parameter, table 2 .....................................11 changes to table 3 ..........................................................................12 change to reflow soldering parameter, table 4.........................15 changes to figure 18, figure 19, figure 20, and figure 21 .......23 changes to figure 25 ......................................................................24 changes to force amplifier section.............................................29 changes to clamps section ...........................................................29 changes to high current ranges section ...................................30 changes to choosing power supply rails section .....................32 changes to compensation capacitors section ...........................33 added table 14, renumbered tables sequentially.....................36 changes to reference selection example ....................................36 changes to table 15 and busy and load functions section ..............................................................................................40 changes to table 17 and register update rates section ...........41 added table 38 ................................................................................57 changes to ordering guide...........................................................60 7/08revision 0: initial version
ad5522 rev. d | page 4 of 64 general description the ad5522 is a high performance, highly integrated parametric measurement unit consisting of four independent channels. each per-pin parametric measurement unit (ppmu) channel includes five 16-bit, voltage output dacs that set the programmable input levels for the force voltage inputs, clamp inputs, and comparator inputs (high and low). five programmable force and measure current ranges are available, ranging from 5 a to 80 ma. four of these ranges use on-chip sense resistors; one high current range up to 80 ma is available per channel using off-chip sense resistors. currents in excess of 80 ma require an external ampli- fier. low capacitance dut connections (fohx and extfohx) ensure that the device is suited to relayless test systems. the pmu functions are controlled via a simple 3-wire serial interface compatible with spi, qspi?, microwire?, and dsp interface standards. interface clocks of 50 mhz allow fast updating of modes. the low voltage differential signaling (lvds) interface protocol at 83 mhz is also supported. comparator outputs are provided per channel for device go-no-go testing and character- ization. control registers allow the user to easily change force or measure conditions, dac levels, and selected current ranges. the sdo (serial data output) pin allows the user to read back information for diagnostic purposes.
ad5522 rev. d | page 5 of 64 dutgnd guard0 cpol0/scl k cpoh0/sdi guardin0/ dutgnd0 dut sys_force sys_sense cgalm cpol2/cpo0 cpol1/sync cpoh1/sdo cpoh2/cpo1 tmpalm clamp and guard alarm temp sensor to measout mux measvh3 foh3 extmeasih3 extmeasil3 ch1 ch0 ch2 ch3 foh2 extfoh2 extmeasih2 extmeasil2 measvh2 guard2 measvh1 extmeasil1 foh1 extfoh1 cff1 cff3 cff2 extmeasih1 guard1 guardin1/dutgnd1 measout1 ccomp1 ccomp2 measout2 agnd agnd dutgnd 16 16 16 measvh0 cpol3/ cpo2 cpoh3/ cpo3 spi/ lvds external r sense (currents up to 80ma) extmeasih0 extmeasil0 foh0 extfoh0 cff0 fin clh cll avss avdd agnd + ? measout0 dgnd cph comparator ccomp0 cpl ? ? ? ? + + ? + ? + + + r sense ? ? + + 16 16 16 16 16 vref dvcc 16 x1 reg c reg m reg 16 16 16 16 16 16 16 16-bit fin dac 5 or 10 2 1 agnd refgnd 16-bit clh dac measout mux and gain 1/0.2 x1 reg c reg m reg x1 reg c reg m reg 2 16 16 16 16 x1 reg c reg m reg 6 6 offset dac force amplifier 16-bit cll dac 16-bit cph dac 16-bit cpl dac sw1 sw2 sw3 sw4 sw6 sw9 sw8 sw5 sw10 sw11 measure voltage in-amp measure current in-amp temp sensor sw12 x1 reg c reg m reg 6 x2 reg x2 reg x2 reg 6 x2 reg x2 reg 6 6 2 2 agnd en guard amp sw13 sw14 agnd 10k ? sw15 sw16 dutgnd vmid to center i range agnd 10k ? agnd 10k ? + ? guardin2/dutgnd2 extfoh3 16 16 16 guardin3/ dutgnd3 guard3 dut external r sense (currents up to 80ma) fin clh cll agnd + ? measout3 cph comparator cpl internal range select (5a, 20a, 200a, 2ma) internal range select (5a, 20a, 200a, 2ma) ? ? ? ? + + ? + ? + + + r sense ? ? + + 16 16 16 16 16 ccomp3 16 x1 reg c reg m reg 16 16 16 16 16 16 16 16-bit fin dac x5 or x10 2 x1 agnd 16-bit clh dac measout mux and gain x1/x0.2 x1 reg c reg m reg x1 reg c reg m reg 2 16 16 16 16 x1 reg c reg m reg 6 6 offset dac force amplifier 16-bit cll dac 16-bit cph dac 16-bit cpl dac sw1 sw2 sw3 sw4 sw6 sw5 sw9 sw8 sw10 sw11 measure voltage in-amp measure current in-amp temp sensor sw12 c reg m reg 6 x2 reg x2 reg x2 reg 6 x2 reg x2 reg 6 6 2 2 en guard amp sw13 sw14 sw15 sw15a sw16 dutgnd vmid to center i range + ? 06197-002 mux mux sclk sync sdi sdo serial interface reset busy 16 power-on reset load 16 16-bit offset dac to all dac output amplifiers x1 reg agnd sw7 4k ? 2k ? 2k ? measvh (hi-z) agnd measvh (hi-z) 4k ? sw7 4k ? 4k ? figure 2. detailed block diagram
ad5522 rev. d | page 6 of 64 specifications avdd 10 v; avss ?5 v; |avdd ? avss| 20 v and 33 v; dvcc = 2.3 v to 5.25 v; vref = 5 v; refgnd = dutgnd = agnd = 0 v; gain (m), offset (c), and dac offset registers at default values; t j = 25c to 90c, unless otherwise noted. (fv = force voltage, fi = force current, mv = measure voltage, mi = measure current, fs = full scale, fsr = full-scale range, fsvr = full-scale voltage range, fscr = full-scale current range.) table 1. parameter min typ 1 max unit test conditions/comments force voltage fohx output voltage range 2 avss + 4 avdd ? 4 v all current ranges from fohx at full-scale current; includes 1 v dropped across sense resistor extfohx output voltage range 2 avss + 3 avdd ? 3 v external high current range at full-scale current; does not include 1 v drop ped across sense resistor output voltage span 22.5 v offset error ?50 +50 mv measured at midscale code; prior to calibration offset error tempco 2 ?10 v/c standard deviation = 20 v/c gain error ?0.5 +0.5 % fsr prior to calibration gain error tempco 2 0.5 ppm/c standard deviation = 0.5 ppm/c linearity error ?0.01 +0.01 % fsr fsr = full-scale range (10 v), gain and offset errors calibrated out short-circuit current limit 2 ?150 +150 ma 80 ma range ?10 +10 ma all other ranges noise spectral density (nsd) 2 320 nv/hz 1 khz, at fohx in fv mode measure current measure current = (i dut r sense gain); amplifier gain = 5 or 10, unless otherwise noted differential input voltage range 2 ?1.125 +1.125 v voltage across r sense ; gain = 5 or 10 output voltage span 22.5 v measure current block with vref = 5 v, measout scaling happens after offset error ?0.5 +0.5 % fscr v(r sense ) = 1 v, measured with zero current flowing offset error tempco 2 1 v/c referred to mi input; standard deviation = 4 v/c gain error ?1 +1 % fscr us ing internal current ranges ?0.5 +0.5 % fscr measure current amplifier alone gain error tempco 2 ?2 ppm/c standard deviation = 2 ppm/c measure current amplifier alon e; internal se nse resistor 25 ppm/c linearity error (measoutx gain = 1) ?0.015 +0.015 % fsr mi gain = 10 ?0.01 +0.01 % fsr mi gain = 5 linearity error (measoutx gain = 0.2) ?0.06 +0.06 % fsr mi gain = 10, avdd = 28 v, avss = ?5 v, offset dac = 0x0 ?0.11 +0.11 % fsr mi gain = 10, avdd = 10 v, avss = ?23 v, offset dac = 0x0edb7 ?0.015 +0.015 % fsr mi gain = 10, avdd = 15.25 v, avss = ?15.25 v, offset dac = 0xa492 ?0.06 +0.06 % fsr mi gain = 5, avdd = 28 v, avss = ?5 v, offset dac = 0x0 ?0.01 +0.01 % fsr mi gain = 5, avdd = 10 v, avss = ?23 v, offset dac = 0xedb7 ?0.01 +0.01 % fsr mi gain = 5, avdd = 15.25 v, avss = ?15.25 v, offset dac = 0xa492 common-mode voltage range 2 avss + 4 avdd ? 4 v common-mode error (gain = 5) ?0.01 +0.01 % fscr/v % of full-scale change at force output per v change in dut voltage common-mode error (gain = 10) ?0.005 +0.005 % fscr/v % of full-scale change at force output per v change in dut voltage sense resistors sense resistors are trimmed to within 1% 200 k 5 a range 50 k 20 a range 5 k 200 a range 0.5 k 2 ma range
ad5522 rev. d | page 7 of 64 parameter min typ 1 max unit test conditions/comments measure current ranges 2 specified current ranges are achieved with vref = 5 v and mi gain = 10, or with vref = 2.5 v and mi gain = 5 5 a set using internal sense resistor 20 a set using internal sense resistor 200 a set using internal sense resistor 2 ma set using internal sense resistor 80 ma set using external se nse resistor; internal amplifier can drive up to 80 ma noise spectral density (nsd) 2 400 nv/hz 1 khz, mi amplifier only, inputs grounded force current voltage compliance, fohx 2 avss + 4 avdd ? 4 v voltage compliance, extfohx 2 avss + 3 avdd ? 3 v offset error ?0.5 +0.5 % fscr measured at midscale code, 0 v, prior to calibration offset error tempco 2 5 ppm fs/c standard deviation = 5 ppm/c gain error ?1.5 +1.5 % fscr prior to calibration gain error tempco 2 ?6 ppm/c standard deviation = 5 ppm/c linearity error ?0.02 +0.02 % fscr common-mode error (gain = 5) ?0.01 +0.01 % fscr/v % of full-scale change per v change in dut voltage common-mode error (gain = 10) ?0.006 +0.006 % fscr/v % of full-scale change per v change in dut voltage force current ranges specified current ranges achieved with vref = 5 v and mi gain = 10, or with vref = 2.5 v and mi gain = 5 v 5 a set using internal sense resistor, 200 k 20 a set using internal sense resistor, 50 k 200 a set using internal sense resistor, 5 k 2 ma set using internal sense resistor, 500 80 ma set using external se nse resistor; internal amplifier can drive up to 80 ma measure voltage measure voltage range 2 avss + 4 avdd ? 4 v offset error ?10 +10 mv gain = 1, measured at 0 v ?25 +25 mv gain = 0.2, measured at 0 v offset error tempco 2 ?1 v/c standard deviation = 6 v/c gain error ?0.25 +0.25 % fsr measoutx gain = 1 ?0.5 +0.5 % fsr measoutx gain = 0.2 gain error tempco 2 1 ppm/c standard deviation = 4 ppm/c linearity error (measoutx gain = 1) ?0.01 +0.01 % fsr linearity error (measoutx gain = 0.2) ?0.01 +0.01 % fsr avdd = 15.25 v, avss = ?15.25 v, offset dac = 0xa492 ?0.06 +0.06 % fsr avdd = 28 v, avss = ?5 v, offset dac = 0x0 ?0.1 +0.1 % fsr avdd = ?10 v, avss = ?23 v, offset dac = 0x3640 noise spectral density (nsd) 2 100 nv/hz 1 khz; measure voltage amplifier only, inputs grounded offset dac span error 30 mv comparator comparator span 22.5 v offset error ?2 +1 +2 mv measured di rectly at comparator; does not include measure block errors offset error tempco 2 1 v/c standard deviation = 2 v/c propagation delay 2 0.25 s voltage clamps clamp span 22.5 v positive clamp accuracy 155 mv negative clamp accuracy ?155 mv cll to clh 2 500 mv cll < clh and minimum voltage apart recovery time 2 0.5 1.5 s activation time 2 1.5 3 s
ad5522 rev. d | page 8 of 64 parameter min typ 1 max unit test conditions/comments current clamps clamp accuracy programmed clamp value programmed clamp value 10 % fsc mi gain = 10, clamp current scales with selected range programmed clamp value programmed clamp value 20 % fsc mi gain = 5, clamp current scales with selected range cll to clh 2 5 % of i range cll < clh and minimum setting apart, mi gain = 10 10 % of i range cll < clh and minimum setting apart, mi gain = 5 recovery time 2 0.5 1.5 s activation time 2 1.5 3 s fohx, extfohx, extmeasilx, extmeasihx, cffx pins pin capacitance 2 10 pf leakage current ?3 +3 na individual pin on or off switch leakage, measured with 11 v stress applied to pin, ch annel enabled, but tristate leakage current tempco 2 0.01 na/c measvhx pin pin capacitance 2 3 pf leakage current ?3 +3 na measured with 11 v stress applied to pin, channel enabled, but tristate leakage current tempco 2 0.01 na/c sys_sense pin sys_sense co nnected, force amplifier inhibited pin capacitance 2 3 pf switch impedance 1 1.3 k leakage current ?3 +3 na measured with 11 v stress applied to pin, switch off leakage current tempco 2 0.01 na/c sys_force pin sys_force co nnected, force amplifier inhibited pin capacitance 2 6 pf switch impedance 60 80 leakage current ?3 +3 na measured with 11 v stress applied to pin, switch off leakage current tempco 2 0.01 na/c combined leakage at dut includes fohx, measvhx, sys_sense, sys_force, extmeasilx, extmeasihx, extfohx, and cffx; calculation of all the individual leakage contributors leakage current ?15 +15 na t j = 25c to 70c ?25 +25 na t j = 25c to 90c leakage current tempco 2 0.1 na/c dutgndx pin voltage range ?500 +500 mv leakage current ?30 +30 na measoutx pin with respect to agnd output voltage span 22.5 v so ftware programmable output range output impedance 60 80 output leakage current ?3 +3 na with sw12 off output capacitance 2 15 pf maximum load capacitance 2 0.5 f output current drive 2 2 ma short-circuit current ?10 +10 ma slew rate 2 2 v/s enable time 2 150 320 ns closing sw12, measured from busy rising edge disable time 2 400 1100 ns opening sw12, measured from busy rising edge mi to mv switching time 2 200 ns measured from busy rising edge; does not include slewing or settling
ad5522 rev. d | page 9 of 64 parameter min typ 1 max unit test conditions/comments guardx pin output voltage span 22.5 v output offset ?10 +10 mv short-circuit current ?15 +15 ma maximum load capacitance 2 100 nf output impedance 85 tristate leakage current 2 ?30 +30 na when guard amplifier is disabled slew rate 2 5 v/s c load = 10 pf alarm activation time 2 200 s alarm delayed to eliminate false alarms force amplifier 2 slew rate 0.4 v/s ccompx = 100 pf, cffx = 220 pf, c load = 200 pf gain bandwidth 1.3 mhz ccompx = 100 pf, cffx = 220 pf, c load = 200 pf max stable load capacitance 10,000 pf ccompx = 100 pf, larger c load requires larger ccomp capacitor 100 nf ccompx = 1 nf, larger c load requires larger ccomp capacitor fv settling time to 0.05% of fs 2 midscale to full-scale change; measured from sync rising edge, clamps on 80 ma range 22 40 s ccompx = 100 pf, cffx = 220 pf, c load = 200 pf 2 ma range 24 40 s ccompx = 100 pf, cffx = 220 pf, c load = 200 pf 200 a range 40 80 s ccompx = 100 pf, cffx = 220 pf, c load = 200 pf 20 a range 300 s ccompx = 100 pf, cffx = 220 pf, c load = 200 pf 5 a range 1400 s ccompx = 100 pf, cffx = 220 pf, c load = 200 pf mi settling time to 0.05% of fs 2 midscale to full-scale change; driven from force amplifier in fv mode, so includes fv settling time; measured from sync rising edge, clamps on 80 ma range 22 40 s ccompx = 100 pf, cffx = 220 pf, c load = 200 pf 2 ma range 24 40 s ccompx = 100 pf, cffx = 220 pf, c load = 200 pf 200 a range 60 100 s ccompx = 100 pf, cffx = 220 pf, c load = 200 pf 20 a range 462 s ccompx = 100 pf, cffx = 220 pf, c load = 200 pf 5 a range 1902 s ccompx = 100 pf, cffx = 220 pf, c load = 200 pf fi settling time to 0.05% of fs 2 midscale to full-scale change; measured from sync rising edge, clamps on 80 ma range 24 55 s ccompx = 100 pf, c load = 200 pf 2 ma range 24 60 s ccompx = 100 pf, c load = 200 pf 200 a range 50 120 s ccompx = 100 pf, c load = 200 pf 20 a range 450 s ccompx = 100 pf, c load = 200 pf 5 a range 2700 s ccompx = 100 pf, c load = 200 pf mv settling time to 0.05% of fs 2 midscale to full-scale change; driven from force amplifier in fv mode, so includes fv settling time; measured from sync rising edge, clamps on 80 ma range 24 55 s ccompx = 100 pf, c load = 200 pf 2 ma range 24 60 s ccompx = 100 pf, c load = 200 pf 200 a range 50 120 s ccompx = 100 pf, c load = 200 pf 20 a range 450 s ccompx = 100 pf, c load = 200 pf 5 a range 2700 s ccompx = 100 pf, c load = 200 pf dac specifications resolution 16 bits output voltage span 2 22.5 v vref = 5 v, within a range of ?16.25 v to +22.5 v differential nonlinearity 2 ?1 +1 lsb guaranteed monotonic by design over temperature comparator dac dynamic specifications 2 output voltage settling time 1 s 500 mv change to ? lsb slew rate 5.5 v/s digital-to-analog glitch energy 20 nv-sec glitch impulse peak amplitude 10 mv reference input vref dc input impedance 1 100 m vref input current ?10 +0.03 +10 a vref range 2 2 5 v
ad5522 rev. d | page 10 of 64 parameter min typ 1 max unit test conditions/comments die temperature sensor accuracy 2 7 c output voltage at 25c 1.5 v output scale factor 2 4.6 mv/c output voltage range 2 0 3 v interaction and crosstalk 2 dc crosstalk (fohx) 0.05 0.65 mv dc change resulting from a dc change in any dac in the device, fv and fi modes, 2 ma range, c load = 200 pf, r load = 5.6 k dc crosstalk (measoutx) 0.05 0.65 mv dc chan ge resulting from a dc change in any dac in the device, mv and mi modes, 2 ma range, c load = 200 pf, r load = 5.6 k dc crosstalk within a channel 0.05 mv all channels in fvmi mode, one channel at midscale; measure the current for one channel in the lowest current range for a change in comparator or clamp dac levels for that pmu spi interface logic inputs input high voltage, v ih 1.7/2.0 v (2.3 v to 2.7 v)/(2.7 v to 5.25 v), jedec-compliant input levels input low voltage, v il 0.7/0.8 v (2.3 v to 2.7 v)/(2.7 v to 5.25 v), jedec-compliant input levels input current, i inh , i inl ?1 +1 a input capacitance, c in 2 10 pf cmos logic outputs sdo, cpox output high voltage, v oh dvcc ? 0.4 v output low voltage, v ol 0.4 v i ol = 500 a tristate leakage current ?2 +2 a sdo, cpoh1/ sdo ?1 +1 a all other output pins output capacitance 2 10 pf open-drain logic outputs busy , tmpalm , cgalm output low voltage, v ol 0.4 v i ol = 500 a, c load = 50 pf, r pullup = 1 k output capacitance 2 10 pf lvds interface logic inputs reduced range link 2 input voltage range 875 1575 mv input differential threshold ?100 +100 mv external termination resistance 80 100 120 differential input voltage 100 mv lvds interface logic outputs reduced range link output offset voltage 1200 mv output differential voltage 400 mv power supplies avdd 10 28 v |avdd ? avss| 33 v avss ?23 ?5 v dvcc 2.3 5.25 v ai dd 26 ma internal ranges (5 a to 2 ma), excluding load conditions; comparators and guard disabled ai ss ?26 ma internal ranges (5 a to 2 ma), excluding load conditions; comparators and guard disabled ai dd 28 ma internal ranges (5 a to 2 ma), excluding load conditions; comparators and guard enabled ai ss ?28 ma internal ranges (5 a to 2 ma), excluding load conditions; comparators and guard enabled ai dd 36 ma external range, excluding load conditions ai ss ?36 ma external range, excluding load conditions di cc 1.5 ma maximum power dissipation 2 7 w maximum power that should be dissipated in this package under worst-case load conditions; careful consideration should be given to supply selection and thermal design
ad5522 rev. d | page 11 of 64 parameter min typ 1 max unit test conditions/comments power supply sensitivity 2 from dc to 1 khz forced voltage/avdd ?80 db forced voltage/avss ?80 db measured current/avdd ?85 db measured current/avss ?75 db forced current/avdd ?75 db forced current/avss ?75 db measured voltage/avdd ?85 db measured voltage/avss ?80 db forced voltage/dvcc ?90 db measured current/dvcc ?90 db forced current/dvcc ?90 db measured voltage/dvcc ?90 db 1 typical specifications are at 25c and nominal supply, 15.25 v, unless otherwise noted. 2 guaranteed by design and characterization; not production tested. tempco values are mean and standard deviation, unless otherw ise noted. timing characteristics avdd 10 v, avss ?5 v, |avdd ? avss| 20 v and 33 v, dvcc = 2.3 v to 5.25 v, vref = 5 v, t j = 25c to 90c, unless otherwise noted. table 2. spi interface dvcc, limit at t min , t max parameter 1 , 2 , 3 2.3 v to 2.7 v 2.7 v to 3.6 v 4.5 v to 5.25 v unit description t write 4 1030 735 735 ns min single channel update cycle time (x1 register write) 950 655 655 ns min single channel update cy cle time (any other register write) t 1 30 20 20 ns min sclk cycle time t 2 8 8 8 ns min sclk high time t 3 8 8 8 ns min sclk low time t 4 10 10 10 ns min sync falling edge to sclk falling edge setup time t 5 4 150 150 150 ns min minimum sync high time in write mode after x1 register write (one channel) 70 70 70 ns min minimum sync high time in write mode after any other register write t 6 10 5 5 ns min 29 th sclk falling edge to sync rising edge t 7 5 5 5 ns min data setup time t 8 9 7 4.5 ns min data hold time t 9 120 75 55 ns max sync rising edge to busy falling edge t 10 busy pulse width low for x1 and some pmu register writes; see and table 17 table 18 1 dac x1 1.65 1.65 1.65 s max 2 dac x1 2.3 2.3 2.3 s max 3 dac x1 2.95 2.95 2.95 s max 4 dac x1 3.6 3.6 3.6 s max other registers 270 270 270 ns max system control register/pmu registers t 11 20 20 20 ns min 29 th sclk falling edge to load falling edge t 12 20 20 20 ns min load pulse width low t 13 150 150 150 ns min busy rising edge to fohx output response time t 14 0 0 0 ns min busy rising edge to load falling edge t 15 100 100 100 ns max load falling edge to fohx output response time
ad5522 rev. d | page 12 of 64 dvcc, limit at t min , t max parameter 1 , 2 , 3 2.3 v to 2.7 v 2.7 v to 3.6 v 4.5 v to 5.25 v unit description t 16 1.8 1.2 0.9 s min reset pulse width low t 17 670 700 750 s max reset time indicated by busy low t 18 400 400 400 ns min minimum sync high time in readback mode t 19 5 , 6 60 45 25 ns max sclk rising edge to sdo valid; dvcc = 5 v to 5.25 v 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with t r = t f = 2 ns (10% to 90% of dvcc) and timed from a voltage level of 1.2 v. 3 see figure 5 and figure 6. 4 writes to more than one x1 register engages the calibration engine for longer times, shown by the busy low time, t 10 . subsequent writes to one or more x1 registers should either be timed or should wait until busy returns high (see figure 56). this is required to ensure that data is not lost or overwritten. 5 t 19 is measured with the load circuit shown in figure 4. 6 sdo output slows with lower dvcc supply and may require use of a slower sclk. table 3. lvds interface dvcc, limit at t min , t max parameter 1 , 2 , 3 2.7 v to 3.6 v 4.5 v to 5.25 v unit description t 1 20 12 ns min sclk cycle time t 2 8 5 ns min sclk pulse width high and low time t 3 3 3 ns min sync to sclk setup time t 4 3 3 ns min data setup time t 5 5 3 ns min data hold time t 6 3 3 ns min sclk to sync hold time t 7 4 45 25 ns min sclk rising edge to sdo valid t 8 150 150 ns min minimum sync high time in write mode after x1 register write 70 70 ns min minimum sync high time in write mode after any other register write 400 400 ns min minimum sync high time in readback mode 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with t r = t f = 2 ns (10% to 90% of dvcc) and timed from a voltage level of 1.2 v. 3 see figure 7. 4 sdo output slows with lower dvcc supply and may require use of slower sclk.
ad5522 rev. d | page 13 of 64 circuit and timing diagrams to output pin dvcc r load 2.2k ? c load 50pf v ol 06197-003 figure 3. load circuit for cgalm , tmpalm 06197-004 v oh (min) ? v ol (max) 2 200a i ol 200a i oh to output pin c load 50pf figure 4. load circuit for sdo, busy timing diagram sync sclk sdi busy reset 11 2 t 3 t 2 29 t 4 t 6 t 5 t 1 t 7 t 8 t 9 db28 (n) db0 (n) db28 (n+1) db0 (n + 1) 29 t 10 t 16 t 17 busy 1 load active during busy. 2 load active after busy. load 1 fohx 1 load 2 fohx 2 t 11 t 12 t 13 t 14 t 12 t 15 06197-005 figure 5. spi write timing (w rite word contains 29 bits)
ad5522 rev. d | page 14 of 64 sclk sync sdi sdo 29 58 db0 (n) db28 (n) db0 (n + 1) db0 (n + 1) input word specifies register to be read undefined nop condition selected register data clocked out t 18 t 19 db23/ db28 (n + 1) db23/ db28 (n + 1) 06197-006 figure 6. spi read timing (readback word contains 24 bits and can be clocked out with a minimum of 24 clock edges) sync sync sclk sdi sdi sclk msb d28 lsb d0 t 3 t 1 t 4 t 2 t 7 t 6 t 5 t 8 sdo lsb d0 msb d23/d28 selected register data clocked out undefined msb db23/ db28 lsb db0 sdo 0 6197-007 figure 7. lvds read and write timing (readback word contains 24 bits and can be clocked out with a minimum of 24 clock edges)
ad5522 rev. d | page 15 of 64 absolute maximum ratings thermal resistance table 4. parameter rating thermal resistance values are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. supply voltage, avdd to avss 34 v avdd to agnd ?0.3 v to +34 v avss to agnd +0.3 v to ?34 v table 5. thermal resistance 1 (jedec 4-layer (1s2p) board) package type airflow (lfpm) ja jc vref to agnd ?0.3 v to +7 v dutgnd to agnd avdd + 0.3 v to avss ? 0.3 v unit refgnd to agnd avdd + 0.3 v to avss ? 0.3 v tqfp exposed pad on bottom 4.8 c/w dvcc to dgnd ?0.3 v to +7 v no heat sink 2 0 22.3 c/w agnd to dgnd ?0.3 v to +0.3 v 200 17.2 c/w digital inputs to dgnd ?0.3 v to dvcc + 0.3 v 500 15.1 c/w analog inputs to agnd avss ? 0.3 v to avdd + 0.3 v with cooling plate at 45c 3 n/a 4 5.4 4.8 c/w storage temperature range ?65c to +125c tqfp exposed pad on top 2 c/w 25c to 90c operating junction temperature range (j version) no heat sink 2 0 42.4 c/w 200 37.2 c/w reflow soldering jedec standard (j-std-020) 500 35.7 c/w junction temperature 150c max with cooling plate at 45c 3 n/a 4 3.0 2 c/w 1 the information in this section is ba sed on simulated thermal information. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 these values apply to the package with no heat sink attached. the actual thermal performance of the package depends on the attached heat sink and environmental conditions. 3 natural convection at 55c ambient. assumes perfect thermal contact between the cooling plate and the exposed paddle. 4 n/a means not applicable. esd caution
ad5522 rev. d | page 16 of 64 pin configurations and function descriptions pin 1 ad5522 top view exposed pad on bottom (not to scale) 1 avdd 2 cff0 3 ccomp0 4 extmeasih0 5 extmeasil0 6 foh0 7 guard0 8 guardin0/dutgnd0 9 measvh0 10 agnd 11 agnd 12 measvh2 13 guardin2/dutgnd2 14 guard2 15 foh2 16 extmeasil2 17 extmeasih2 18 ccomp2 19 cff2 20 avdd 21 extfoh2 22 avss 23 busy 24 sclk 25 cpol0/sclk 26 cpoh0/sdi 27 sdi 28 sync 29 cpol1/sync 30 dgnd 31 cpoh1/sdo sdo 32 33 load 34 dvcc 35 cpol2/cpo0 36 cpoh2/cpo1 37 cpol3/cpo2 38 cpoh3/cpo3 39 avss 40 extfoh3 61 extfoh1 62 avss 63 measout3 64 measout2 65 measout1 66 measout0 67 avss 68 sys_force 69 agnd 70 sys_sense 71 refgnd 72 vref 73 dutgnd 74 avdd 75 spi/lvds 76 cgalm 77 tmpalm 78 reset 79 avss 80 extfoh0 41 avdd 42 cff3 43 ccomp3 44 extmeasih3 45 extmeasil3 46 foh3 47 guard3 48 guardin3/dutgnd3 49 measvh3 50 agnd 51 agnd 52 measvh1 53 guardin1/dutgnd1 54 guard1 55 foh1 56 extmeasil1 57 extmeasih1 58 ccomp1 59 cff1 60 avdd 06197-008 notes 1. the exposed pad is internally electrically connected to avss. for enhanced thermal, electrical, and board level performance, the exposed paddle on the bottom of the package should be soldered to a corresponding thermal land paddle on the pcb. figure 8. pin configuration, exposed pad on bottom table 6. pin function descriptions pin no. mnemonic description exposed pad the exposed pad is internally electrically connected to avss. for enhanced thermal, electrical, and board level performance, the exposed paddle on the bottom of th e package should be soldered to a corresponding thermal land paddle on the pcb. 1, 20, 41, 60, 74 avdd positive analog supply voltage. 2 cff0 external capacitor for channel 0. this pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. see the compensation capacitors section. 3 ccomp0 compensation capacitor input for channel 0. see the compensation capacitors section. 4 extmeasih0 sense input (high sense) for high current range (channel 0). 5 extmeasil0 sense input (low sense) for high current range (channel 0). 6 foh0 force output for internal current ranges (channel 0). 7 guard0 guard output drive for channel 0. 8 guardin0/ dutgnd0 guard amplifier input for channel 0/dutgnd input for cha nnel 0. this dual function pin is configured via the serial interface. the default function at power-on is gu ardin0. if this pin is configured as a dutgnd input for the channel, the input to the guard am plifier is internally connected to measvh0. for more information, see the device under test ground (dutgnd) section and the guard amplifier section. 9 measvh0 dut voltage sense input (high sense) for channel 0. 10, 11, 50, 51, 69 agnd analog ground. these pins are the reference points for the analog supplies and the measure circuitry. 12 measvh2 dut voltage sense input (high sense) for channel 2.
ad5522 rev. d | page 17 of 64 pin no. mnemonic description 13 guardin2/ dutgnd2 guard amplifier input for channel 2/dutgnd input for cha nnel 2. this dual function pin is configured via the serial interface. the default function at power-on is gu ardin2. if this pin is configured as a dutgnd input for the channel, the input to the guard am plifier is internally connected to measvh2. for more information, see the device under test ground (dutgnd) section and the guard amplifier section. 14 guard2 guard output drive for channel 2. 15 foh2 force output for internal current ranges (channel 2). 16 extmeasil2 sense input (low sense) for high current range (channel 2). 17 extmeasih2 sense input (high sense) for high current range (channel 2). 18 ccomp2 compensation capacitor input for channel 2. see the compensation capacitors section. 19 cff2 external capacitor for channel 2. this pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. see the compensation capacitors section. 21 extfoh2 force output for high current range (channel 2). use an external resistor at this pin for current ranges up to 80 ma. for more information, see the current range selection section. 22, 39, 62, 67, 79 avss negative analog supply voltage. 23 busy digital input/open-drain output. this pin in dicates the status of the interface. see the busy and load functions section for more information. 24 sclk serial clock input, active falling edge. data is clocked into the shift register on the falling edge of sclk. this pin operates at clock speeds up to 50 mhz. 25 cpol0/ sclk comparator output low (channel 0) for spi interface/di fferential serial clock input (complement) for lvds interface. 26 cpoh0/ sdi comparator output high (channel 0) for spi interface/di fferential serial data input (complement) for lvds interface. 27 sdi serial data input for spi or lvds interface. 28 sync active low frame synchronization input for spi or lvds interface. 29 cpol1/sync comparator output low (channel 1) for spi interface/differential sync input for lvds interface. 30 dgnd digital ground reference point. 31 cpoh1/ sdo comparator output high (channel 1) for spi interface/di fferential serial data o utput (complement) for lvds interface. 32 sdo serial data output for spi or lvds interface. this pi n can be used for data readback and diagnostic purposes. 33 load logic input (active low). this pin synchronizes update s within one device or across a group of devices. if synchronization is not required, load can be tied low; in this case, dac channels and pmu modes are updated immediately after busy goes high. see the busy and load functions section for more information. 34 dvcc digital supply voltage. 35 cpol2/cpo0 comparator output low (channel 2) for spi interface/comparator output window (channel 0) for lvds interface. 36 cpoh2/cpo1 comparator output high (channel 2) for spi interfac e/comparator output window (channel 1) for lvds interface. 37 cpol3/cpo2 comparator output low (channel 3) for spi interface/comparator output window (channel 2) for lvds interface. 38 cpoh3/cpo3 comparator output high (channel 3) for spi interfac e/comparator output window (channel 3) for lvds interface. 40 extfoh3 force output for high current range (channel 3). use an external resistor at this pin for current ranges up to 80 ma. for more information, see the current range selection section. 42 cff3 external capacitor for channel 3. this pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. see the compensation capacitors section. 43 ccomp3 compensation capacitor input for channel 3. see the compensation capacitors section. 44 extmeasih3 sense input (high sense) for high current range (channel 3). 45 extmeasil3 sense input (low sense) for high current range (channel 3). 46 foh3 force output for internal current ranges (channel 3). 47 guard3 guard output drive for channel 3. 48 guardin3/ dutgnd3 guard amplifier input for channel 3/dutgnd input for cha nnel 3. this dual function pin is configured via the serial interface. the default function at power-on is gu ardin3. if this pin is configured as a dutgnd input for the channel, the input to the guard am plifier is internally connected to measvh3. for more information, see the device under test ground (dutgnd) section and the guard amplifier section.
ad5522 rev. d | page 18 of 64 pin no. mnemonic description 49 measvh3 dut voltage sense input (high sense) for channel 3. 52 measvh1 dut voltage sense input (high sense) for channel 1. 53 guardin1/ dutgnd1 guard amplifier input for channel 1/dutgnd input for cha nnel 1. this dual function pin is configured via the serial interface. the default function at power-on is gu ardin1. if this pin is configured as a dutgnd input for the channel, the input to the guard am plifier is internally connected to measvh1. for more information, see the device under test ground (dutgnd) section and the guard amplifier section. 54 guard1 guard output drive for channel 1. 55 foh1 force output for internal current ranges (channel 1). 56 extmeasil1 sense input (low sense) for high current range (channel 1). 57 extmeasih1 sense input (high sense) for high current range (channel 1). 58 ccomp1 compensation capacitor input for channel 1. see the compensation capacitors section. 59 cff1 external capacitor for channel 1. this pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. see the compensation capacitors section. 61 extfoh1 force output for high current range (channel 1). use an external resistor at this pin for current ranges up to 80 ma. for more information, see the current range selection section. 63 measout3 multiplexed dut voltage, current sense output, temper ature sensor voltage for channel 3. this pin is referenced to agnd. 64 measout2 multiplexed dut voltage, current sense output, temper ature sensor voltage for channel 2. this pin is referenced to agnd. 65 measout1 multiplexed dut voltage, current sense output, temper ature sensor voltage for channel 1. this pin is referenced to agnd. 66 measout0 multiplexed dut voltage, current sense output, temper ature sensor voltage for channel 0. this pin is referenced to agnd. 68 sys_force external force signal input. this pin enables the connection of the system pmu. 70 sys_sense external sense signal output. this pin enables the connection of the system pmu. 71 refgnd accurate analog reference input ground. 72 vref reference input for dac channels (5 v for specified performance). 73 dutgnd dut voltage sense input (low sense). by default, this in put is shared among all four pmu channels. if a dutgnd input is required for each channel, the user can conf igure the guardinx/dutgndx pins as dutgnd inputs for each pmu channel. 75 spi /lvds interface select pin. logic low selects spi-compatible interface mode; logic high selects lvds interface mode. this pin has a pull-down current source (~350 a). in lvds interface mode, the cpohx and cpolx pins default to differential interface pins. 76 cgalm open-drain output for guard and clamp alarms. this open-drain pin provides shared alarm information about the guard amplifier and clamp circuitry. by defa ult, this output pin is disabled. the system control register allows the user to enable this function and to set the open-drain output as a latched output. the user can also choose to enable alarms for the guard amplifier, the clamp circuitry, or both. when this pin flags an alarm, the origins of the alarm can be determined by reading back the alarm status register. two flags per channel in this word (one latched, one unlatched) indicate which functi on caused the alarm and whether the alarm is still present. 77 tmpalm open-drain output for temperature alarm. this latche d, active low, open-drain output flags a temperature alarm to indicate that the junction temperature has ex ceeded the default temperature setting (130c) or the user programmed temperature setting. two flags in the alarm status register (one latched, one unlatched) indicate whether the temperature has dropped below 130 c or remains above 130c. user action is required to clear this latched alarm flag by writing to the clear bit (bit 6) in any of the pmu registers. 78 reset digital reset input. this active low, level sensitive inp ut resets all internal nodes on the device to their power- on reset values. 80 extfoh0 force output for high current range (channel 0). use an external resistor at this pin for current ranges up to 80 ma. for more information, see the current range selection section.
ad5522 rev. d | page 19 of 64 pin 1 ad5522 top view exposed pad on top (not to scale) 1 avdd 2 cff0 3 ccomp0 4 extmeasih0 5 extmeasil0 6 foh0 7 guard0 8 guardin0/dutgnd0 9 measvh0 10 agnd 11 agnd 12 measvh2 13 guardin2/dutgnd2 14 guard2 15 foh2 16 extmeasil2 17 extmeasih2 18 ccomp2 19 cff2 20 avdd 21 extfoh2 22 avss 23 busy 24 sclk 25 cpol0/sclk 26 cpoh0/sdi 27 sdi 28 sync 29 cpol1/sync 30 dgnd 31 cpoh1/sdo sdo 32 33 load 34 dvcc 35 cpol2/cpo0 36 cpoh2/cpo1 37 cpol3/cpo2 38 cpoh3/cpo3 39 avss 40 extfoh3 61 extfoh1 62 avss 63 measout3 64 measout2 65 measout1 66 measout0 67 avss 68 s ys_force 69 agnd 70 sys_sense 71 refgnd 72 vref 73 dutgnd 74 avdd 75 spi/lvds 76 cgalm 77 tmpalm 78 reset 79 avss 80 extfoh0 41 avdd 42 cff3 43 ccomp3 44 extmeasih3 45 extmeasil3 46 foh3 47 guard3 48 guardin3/dutgnd3 49 measvh3 50 agnd 51 agnd 52 measvh1 53 guardin1/dutgnd1 54 guard1 55 foh1 56 extmeasil1 57 extmeasih1 58 ccomp1 59 cff1 60 avdd 06197-009 notes 1. the exposed pad is electrically connected to avss. figure 9. pin configuration, exposed pad on top table 7. pin function descriptions pin no. mnemonic description exposed pad the exposed pad is electrically connected to avss. 1 extfoh0 force output for high current range (channel 0). use an external resistor at this pin for current ranges up to 80 ma. for more information, see the current range selection section. 2, 14, 19, 42, 59 avss negative analog supply voltage. 3 reset digital reset input. this active low, level sensitive inp ut resets all internal nodes on the device to their power- on reset values. 4 tmpalm open-drain output for temperature alarm. this latche d, active low, open-drain output flags a temperature alarm to indicate that the junction temperature has ex ceeded the default temperature setting (130c) or the user programmed temperature setting. two flags in the alarm status register (one latched, one unlatched) indicate whether the temperature has dropped below 130 c or remains above 130c. user action is required to clear this latched alarm flag by writing to the clear bit (bit 6) in any of the pmu registers. 5 cgalm open-drain output for guard and clamp alarms. this open-drain pin provides shared alarm information about the guard amplifier and clamp circuitry. by defa ult, this output pin is disabled. the system control register allows the user to enable this function and to set the open-drain output as a latched output. the user can also choose to enable alarms for the guard amplifier, the clamp circuitry, or both. when this pin flags an alarm, the origins of the alarm can be determined by reading back the alarm status register. two flags per channel in this word (one latched, one unlatched) indicate which functi on caused the alarm and whether the alarm is still present.
ad5522 rev. d | page 20 of 64 pin no. mnemonic description 6 spi /lvds interface select pin. logic low selects spi-compatible interface mode; logic high selects lvds interface mode. this pin has a pull-down current source (~350 a). in lvds interface mode, the cpohx and cpolx pins default to differential interface pins. 7, 21, 40, 61, 80 avdd positive analog supply voltage. 8 dutgnd dut voltage sense input (low sense). by default, this in put is shared among all four pmu channels. if a dutgnd input is required for each channel, the user can conf igure the guardinx/dutgndx pins as dutgnd inputs for each pmu channel. 9 vref reference input for dac channels. 5 v for specified performance. 10 refgnd accurate analog reference input ground. 11 sys_sense external sense signal output. this pin enables the connection of the system pmu. 12, 30, 31, 70, 71 agnd analog ground. these pins are the reference points for the analog supplies and the measure circuitry. 13 sys_force external force signal input. this pin enables the connection of the system pmu. 15 measout0 multiplexed dut voltage, current sense output, temper ature sensor voltage for channel 0. this pin is referenced to agnd. 16 measout1 multiplexed dut voltage, current sense output, temper ature sensor voltage for channel 1. this pin is referenced to agnd. 17 measout2 multiplexed dut voltage, current sense output, temper ature sensor voltage for channel 2. this pin is referenced to agnd. 18 measout3 multiplexed dut voltage, current sense output, temper ature sensor voltage for channel 3. this pin is referenced to agnd. 20 extfoh1 force output for high current range (channel 1). use an external resistor at this pin for current ranges up to 80 ma. for more information, see the current range selection section. 22 cff1 external capacitor for channel 1. this pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. see the compensation capacitors section. 23 ccomp1 compensation capacitor input for channel 1. see the compensation capacitors section. 24 extmeasih1 sense input (high sense) for high current range (channel 1). 25 extmeasil1 sense input (low sense) for high current range (channel 1). 26 foh1 force output for internal current ranges (channel 1). 27 guard1 guard output drive for channel 1. 28 guardin1/ dutgnd1 guard amplifier input for channel 1/dutgnd input for cha nnel 1. this dual function pin is configured via the serial interface. the default function at power-on is gu ardin1. if this pin is configured as a dutgnd input for the channel, the input to the guard am plifier is internally connected to measvh1. for more information, see the device under test ground (dutgnd) section and the guard amplifier section. 29 measvh1 dut voltage sense input (high sense) for channel 1. 32 measvh3 dut voltage sense input (high sense) for channel 3. 33 guardin3/ dutgnd3 guard amplifier input for channel 3/dutgnd input for cha nnel 3. this dual function pin is configured via the serial interface. the default function at power-on is gu ardin3. if this pin is configured as a dutgnd input for the channel, the input to the guard am plifier is internally connected to measvh3. for more information, see the device under test ground (dutgnd) section and the guard amplifier section. 34 guard3 guard output drive for channel 3. 35 foh3 force output for internal current ranges (channel 3). 36 extmeasil3 sense input (low sense) for high current range (channel 3). 37 extmeasih3 sense input (high sense) for high current range (channel 3). 38 ccomp3 compensation capacitor input for channel 3. see the compensation capacitors section. 39 cff3 external capacitor for channel 3. this pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. see the compensation capacitors section. 41 extfoh3 force output for high current range (channel 3). use an external resistor at this pin for current ranges up to 80 ma. for more information, see the current range selection section. 43 cpoh3/cpo3 comparator output high (channel 3) for spi interfac e/comparator output window (channel 3) for lvds interface. 44 cpol3/cpo2 comparator output low (channel 3) for spi interface/comparator output window (channel 2) for lvds interface. 45 cpoh2/cpo1 comparator output high (channel 2) for spi interfac e/comparator output window (channel 1) for lvds interface.
ad5522 rev. d | page 21 of 64 pin no. mnemonic description 46 cpol2/cpo0 comparator output low (channel 2) for spi interface/comparator output window (channel 0) for lvds interface. 47 dvcc digital supply voltage. 48 load logic input (active low). this pin synchronizes update s within one device or across a group of devices. if synchronization is not required, load can be tied low; in this case, dac channels and pmu modes are updated immediately after busy goes high. see the busy and load functions section for more information. 49 sdo serial data output for spi or lvds interface. this pi n can be used for data readback and diagnostic purposes. 50 cpoh1/ sdo comparator output high (channel 1) for spi interface/di fferential serial data o utput (complement) for lvds interface. 51 dgnd digital ground reference point. 52 cpol1/sync comparator output low (channel 1) for spi interface/differential sync input for lvds interface. 53 sync active low frame synchronization input for spi or lvds interface. 54 sdi serial data input for spi or lvds interface. 55 cpoh0/ sdi comparator output high (channel 0) for spi interface/di fferential serial data input (complement) for lvds interface. 56 cpol0/ sclk comparator output low (channel 0) for spi interface/di fferential serial clock input (complement) for lvds interface. 57 sclk serial clock input, active falling edge. data is clocked into the shift register on the falling edge of sclk. this pin operates at clock speeds up to 50 mhz. 58 busy digital input/open-drain output. this pin in dicates the status of the interface. see the busy and load functions section for more information. 60 extfoh2 force output for high current range (channel 2). use an external resistor at this pin for current ranges up to 80 ma. for more information, see the current range selection section. 62 cff2 external capacitor for channel 2. this pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. see the compensation capacitors section. 63 ccomp2 compensation capacitor input for channel 2. see the compensation capacitors section. 64 extmeasih2 sense input (high sense) for high current range (channel 2). 65 extmeasil2 sense input (low sense) for high current range (channel 2). 66 foh2 force output for internal current ranges (channel 2). 67 guard2 guard output drive for channel 2. 68 guardin2/ dutgnd2 guard amplifier input for channel 2/dutgnd input for cha nnel 2. this dual function pin is configured via the serial interface. the default function at power-on is gu ardin2. if this pin is configured as a dutgnd input for the channel, the input to the guard am plifier is internally connected to measvh2. for more information, see the device under test ground (dutgnd) section and the guard amplifier section. 69 measvh2 dut voltage sense input (high sense) for channel 2. 72 measvh0 dut voltage sense input (high sense) for channel 0. 73 guardin0/ dutgnd0 guard amplifier input for channel 0/dutgnd input for cha nnel 0. this dual function pin is configured via the serial interface. the default function at power-on is gu ardin0. if this pin is configured as a dutgnd input for the channel, the input to the guard am plifier is internally connected to measvh0. for more information, see the device under test ground (dutgnd) section and the guard amplifier section. 74 guard0 guard output drive for channel 0. 75 foh0 force output for internal current ranges (channel 0). 76 extmeasil0 sense input (low sense) for high current range (channel 0). 77 extmeasih0 sense input (high sense) for high current range (channel 0). 78 ccomp0 compensation capacitor input for channel 0. see the compensation capacitors section. 79 cff0 external capacitor for channel 0. this pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. see the compensation capacitors section.
ad5522 rev. d | page 22 of 64 typical performance characteristics 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 60,000 50,000 40,000 30,000 20,000 10,000 0 06197-010 linearity (lsb) code dnl inl t a = 25c figure 10. force voltage linearity vs. code, all ranges, 1 lsb = 0.0015% fsr (20 v fsr) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 linearity (lsb) 60,000 50,000 40,000 30,000 20,000 10,000 0 06197-011 code dnl inl t a = 25c figure 11. force current linearity vs. code, all ranges, 1 lsb = 0.0015% fsr (20 v fsr) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 60,000 50,000 40,000 30,000 20,000 10,000 0 06197-012 linearity (lsb) code dnl inl t a = 25c figure 12. measure voltage linearity vs. code, all ranges, 1 lsb = 0.0015% fsr (20 v fsr), measoutx gain = 1 0.0020 ?0.0005 0 0.0005 0.0010 0.0015 0 10,000 20,000 30,000 40,000 50,000 60,000 linearity (% fsr) code 06197-140 nom: avdd = +16.5v, avss = ?16.6v, offset dac = 0xa492 high: avdd = +28v, avss = ?5v, offset dac = 0x0 low: avdd = +10v, avss = ?23v, offset dac = 0xedb7 figure 13. measure voltage linearity vs. code, all ranges, measoutx gain = 0.2 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 60,000 50,000 40,000 30,000 20,000 10,000 0 06197-013 linearity (lsb) code dnl inl t a = 25c figure 14. measure current line arity vs. code, all ranges, 1 lsb = 0.0015% fsr (20 v fsr), mi gain = 10, measoutx gain = 1 0.035 ?0.001 ?0.005 0 0.005 0.010 0.015 0.020 0.025 0.030 0 10,000 20,000 30,000 40,000 50,000 60,000 linearity (% fsr) code 06197-141 avdd = +15.5v, avss = ?15.5v, offset dac = 0xa492 avdd = +28v, avss = ?5v, offset dac = 0x0 avdd = +10v, avss = ?23v, offset dac = 0xedb7 figure 15. measure current line arity vs. code, all ranges, measoutx gain = 0.2, mi gain = 10
ad5522 rev. d | page 23 of 64 0.005 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 0 10,000 20,000 30,000 40,000 50,000 60,000 linearity (% fsr) code 06197-142 avdd = +15.5v, avss = ?15.5v, offset dac = 0xa492 avdd = +28v, avss = ?5v, offset dac = 0x0 avdd = +10v, avss = ?23v, offset dac = 0xed87 figure 16. measure current line arity vs. code, all ranges, measoutx gain = 0.2, mi gain = 5 1.0 0.8 0.6 0.4 0.2 0 ?0.2 25 35 45 55 65 75 85 95 06197-014 leakage current (na) temperature (c) extfohx cffx fohx extmeasihx extmeasilx measvhx guardinx/dutgndx combined leakage v = 0v figure 17. leakage current vs. temperature (stress voltage = 0 v) 2.0 1.5 1.0 0.5 0 ?0.5 25 35 45 55 65 75 85 95 06197-015 leakage current (na) temperature (c) extfohx cffx fohx extmeasihx extmeasilx measvhx guardinx/dutgndx combined leakage v = 12v figure 18. leakage current vs. temperature (stress voltage = 12 v) 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 25 35 45 55 65 75 85 95 06197-016 leakage current (na) temperature (c) extfohx cffx fohx extmeasihx extmeasilx measvhx guardinx/dutgndx combined leakage v = ?12v figure 19. leakage current vs. temperature (stress voltage = ?12 v) 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 06197-017 leakage current (na) stress voltage (v) extfohx cffx fohx extmeasihx extmeasilx measvhx guardinx/dutgndx combined leakage t a = 25c figure 20. leakage current vs. stress voltage 0 ?20 ?40 ?60 ?80 ?100 ?120 10 10m 100 acpsrr (db) 10k 100k 1m 1k frequency (hz) 06197-018 avdd acpsrr avss acpsrr dvcc acpsrr figure 21. acpsrr at fohx in fo rce voltage mode vs. frequency
ad5522 rev. d | page 24 of 64 10 1m 100 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 acpsrr (db) 10k 100k 1k frequency (hz) 06197-019 v ss v dd v cc figure 22. acpsrr at fohx in for ce current mode vs. frequency (mi gain = 10) 10 1m 100 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 acpsrr (db) 10k 100k 1k frequency (hz) 06197-119 v ss v dd v cc figure 23. acpsrr at fohx in fo rce current mode vs. frequency (mi gain = 5) 10 1m 100 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 acpsrr (db) 10k 100k 1k frequency (hz) 06197-020 v ss v dd v cc figure 24. acpsrr at measoutx in measure voltage mode vs. frequency (measout gain = 1) 10 1m 100 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 acpsrr (db) 10k 100k 1k frequency (hz) 06197-120 v ss v dd v cc figure 25. acpsrr at measoutx in measure voltage mode vs. frequency (measout gain = 0.2) 10 1m 100 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 acpsrr (db) 10k 100k 1k frequency (hz) 0 6197-021 v ss v dd v cc figure 26. acpsrr at measoutx in measure current mode vs. frequency (mi gain = 10, measout gain = 1) 10 1m 100 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 acpsrr (db) 10k 100k 1k frequency (hz) 0 6197-121 v ss v dd v cc figure 27. acpsrr at measoutx in measure current mode vs. frequency (mi gain = 5, measout gain = 1)
ad5522 rev. d | page 25 of 64 10 1m 100 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 acpsrr (db) 10k 100k 1k frequency (hz) 0 6197-122 v ss v dd v cc figure 28. apcsrr at measoutx in measure current mode vs. frequency (mi gain = 10, measout gain = 0.2) 10 1m 100 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 acpsrr (db) 10k 100k 1k frequency (hz) 0 6197-123 v ss v dd v cc figure 29. apcsrr at measoutx in measure current mode vs. frequency (mi gain = 5, measout gain = 0.2) 900 800 700 600 500 400 300 200 100 0 10 100 1k 10k 100k 1m 06197-022 nsd (nv/ hz) frequency (hz) measure current in-amp measure voltage in-amp force amp figure 30. nsd vs. frequency (mea sured in fvmv and fvmi mode) 06197-023 ch1 20.0mv b w ch2 100mv b w ch1 pk-pk 39.00mv ch2 pk-pk 325.8mv ch4 5.00v m4.00s 1 4 2 t 10.0000s t a = 25c foh0 measout0 load figure 31. ac crosstalk, fvmi mode, pmu 0, full-scale transition on one cph dac, mi gain = 10, measout gain = 1, 2 ma range, c load = 200 pf 06197-024 ch1 20.0mv b w ch2 100mv b w m4.00s 1 4 2 t 10.0000s t a = 25c foh1 measout1 load ch1 pk-pk 18.80mv ch2 pk-pk 140.0mv ch4 5.00v figure 32. ac crosstalk, fvmi mode, pmu 1, full-scale transition on one cph dac, mi gain = 10, measout gain = 1, 2 ma range, c load = 200 pf 06197-025 ch1 10mv b w m10s 1 1 1 t 30.0s t attack from fin1 16.70mv p-p foh0 foh0 foh0 attack from fin2 10.35mv p-p attack from fin3 11.75mv p-p figure 33. ac crosstalk at foh0 in fi mode from fin dac of each other pmu (full- scale transition), mi gain = 10, measout gain = 1, 2 ma range, c load = 200 pf
ad5522 rev. d | page 26 of 64 06197-026 ch1 10.0mv b w ch2 50.0mv b w m100s 1 4 2 3 t 200.000s t a = 25c fohx victim measoutx victim measoutx attack trigger ch2 pk-pk 14.38mv ch4 5.00v ch3 5.00v figure 34. shorted dut ac crosstalk, victim pmu in fvmi mode (200 a range) 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 25 45 35 65 55 75 85 06197-127 measoutx voltage (v) forced temperature (c) nominal supplies 15.25v 5 different devices figure 35. temperature sensor voltage on measoutx vs. forced temperature 06197-128 ch1 100mv b w m2.00s 3 4 1 1 t 6.0000s ch3 5.00v b w ch4 5.00v b w ch4 2.10v foh0 busy sync figure 36. range change, pmu0, 5 a to 2 ma, c load = 1 nf, r load = 620 k, fv = 3 v 06197-129 ch1 50.0mv b w m800ns 4 1 3 t 2.40000s ch3 5.00v b w ch4 5.00v b w ch4 2.10v foh0 busy sync figure 37. range change, pm u0, 2 ma to 5 a, c load = 1 nf, r load = 620 k, fv = 3 v 06197-130 ch1 20.0mv b w m20.0s 4 1 3 t 60.0000s ch3 5.00v b w ch4 5.00v b w ch4 2.10v foh0 busy sync figure 38. range change, pmu0, 5 a to 2 ma, c load = 100 nf, r load = 620 k, fv = 3 v 06197-131 ch1 20.0mv b w m20.0s 4 1 3 t 60.0000s ch3 5.00v b w ch4 5.00v b w ch4 2.10v foh0 busy sync figure 39. range change, pm u0, 2 ma to 5 a, c load = 100 nf, r load = 620 k, fv = 3 v
ad5522 rev. d | page 27 of 64 06197-132 ch1 100.0mv b w m2.00s 4 1 3 t 6.00000s ch3 5.00v b w ch4 5.00v b w ch4 2.10v foh0 busy sync figure 40. range change, pmu0, 20 a to 2 ma, c load = 1 nf, r load = 150 k, fv = 3 v 06197-133 ch1 50.0mv b w m2.000s 4 1 3 t 6.00000s ch3 5.00v b w ch4 5.00v b w ch4 2.10v foh0 busy sync figure 41. range change, pm u0, 2 ma to 20 a, c load = 1 nf, r load = 150 k, fv = 3 v 06197-134 ch1 2.00v ch2 2.00v m10.0s 4 1 2 3 ch3 5.00v ch4 5.00v ch1 3.84v measoutx (mi) busy sync fohx figure 42. fv settling, 0 v to 5 v, 2 ma range, c load = 220 pf, ccompx = 1 nf, r load = 5.6 k 06197-135 ch1 2.00v ch2 2.00v m5.0s 4 1 2 3 ch3 5.00v ch4 5.00v ch1 3.84v busy sync measoutx (mi) fohx figure 43. fv settling, 0 v to 5 v, 2 ma range, c load = 220 pf, ccompx = 100 pf, r load = 5.6 k 06197-136 ch1 2.00v ch2 10.00v m100s 4 1 2 3 ch3 5.00v ch4 5.00v ch1 3.20v busy sync measoutx (mi) fohx figure 44. fv settling, 0 v to 5 v, 5 a range, c load = 220 pf, ccompx = 100 pf, r load = 1 m 06197-137 ch1 2.00v ch2 10.0v m25.0s 4 1 2 3 ch3 5.00v ch4 5.00v ch1 3.20v busy sync measoutx (mi) fohx figure 45. fv settling, 0 v to 5 v, 20 a range, c load = 220 pf, ccompx = 100 pf, r load = 270 k
ad5522 rev. d | page 28 of 64 06197-138 ch1 2.00v ch2 10.0v m10.0s 4 1 2 3 ch3 5.00v ch4 5.00v ch1 3.20v busy sync measoutx (mi) fohx figure 46. fv settling, 0 v to 5 v, 200 a range, c load = 220 pf, ccompx = 100 pf, r load = 27 k
ad5522 rev. d | page 29 of 64 terminology offset error offset error is a measure of the difference between the actual voltage and the ideal voltage at midscale or at zero current expressed in mv or % fsr. gain error gain error is the difference between full-scale error and zero- scale error. it is expressed in % fsr. gain error = full-scale error ? zero-scale error where: full-scale error is the difference between the actual voltage and the ideal voltage at full scale. zero-scale error is the difference between the actual voltage and the ideal voltage at zero scale. linearity error linearity error, or relative accuracy, is a measure of the maximum deviation from a straight line passing through the endpoints of the full-scale range. it is measured after adjusting for gain error and offset error and is expressed in % fsr. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. common-mode (cm) error common-mode (cm) error is the error at the output of the amplifier due to the common-mode input voltage. it is expressed in % of fsvr/v. leakage current leakage current is the current measured at an output pin when that function is off or high impedance. pin capacitance pin capacitance is the capacitance measured at a pin when that function is off or high impedance. slew rate the slew rate is the rate of change of the output voltage expressed in v/s. output voltage settling time output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a full-scale input change. digital-to-analog glitch energy digital-to-analog glitch energy is the amount of energy that is injected into the analog output at the major code transition. it is specified as the area of the glitch in nv-sec. it is measured by toggling the dac register data between 0x7fff and 0x8000. digital crosstalk digital crosstalk is defined as the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter. it is specified in nv-sec. ac crosstalk ac crosstalk is defined as the glitch impulse transferred to the output of one pmu due to a change in any of the dac registers in the package. acpsrr acpsrr is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.2 v p-p. the ratio of the amplitude of the signal on the output to the amplitude of the modulation is the acpsrr.
ad5522 rev. d | page 30 of 64 theory of operation the ad5522 is a highly integrated, quad per-pin parametric measurement unit (ppmu) for use in semiconductor automated test equipment. it provides programmable modes to force a pin voltage and measure the corresponding current (fvmi) and to force a pin current and measure the corresponding voltage (fimv). the device is also capable of all other combinations, including force high-z and measure high-z. the ppmu can force or measure a voltage range of 22.5 v. it can force or measure currents up to 80 ma per channel using the internal amplifier; the addition of an external amplifier enables higher current ranges. all the dac levels required for each pmu channel are on chip. force amplifier the force amplifier drives the analog output, fohx, which drives a programmed current or voltage to the device under test (dut). headroom and footroom requirements for this amplifier are 3 v on either end. an additional 1 v is dropped across the sense resistor when maximum (rated) current is flowing through it. the force amplifier is designed to drive dut capacitances up to 10 nf, with a compensation value of 100 pf. larger dut capacitive loads require larger compensation capacitances. local feedback ensures that the amplifiers are stable when disabled. a disabled channel reduces power consumption by 2.5 ma per channel. comparators per channel, the dut measured voltage or current is monitored by two comparators configured as window comparators. internal dac levels set the cpl (comparator low) and cph (comparator high) threshold values. there are no restrictions on the voltage settings of the comparator highs and lows. cpl going higher than cph is not a useful operation; however, it does not cause any problems with the device. cpolx (comparator output low) and cpohx (comparator output high) are continuous time comparator outputs. table 8. comparator output function using spi interface test condition cpolx cpohx v dut or i dut > cph 0 v dut or i dut < cph 1 v dut or i dut > cpl 1 v dut or i dut < cpl 0 cph > v dut or i dut > cpl 1 1 when using the spi interface, full comparator functionality is available. when using the lvds interface, the comparator function is limited to one output per comparator, due to the large pin count requirement of the lvds interface. when using the lvds interface, the comparator output available pins, cpo0 to cpo3, provide information on whether the meas- ured voltage or current is inside or outside the set cph and cpl window. information on whether the measurement was high or low is available via the serial interface (comparator status register). table 9. comparator output function using lvds interface test condition cpox output (cpl < (v dut or i dut )) and ((v dut or i dut ) < cph) 1 (cpl > (v dut or i dut )) or ((v dut or i dut ) > cph) 0 clamps current and voltage clamps are included on chip, one clamp for each pmu channel. the clamps protect the dut in the event of an open-circuit or short-circuit condition. internal dac levels set the cll (clamp low) and clh (clamp high) levels. the clamps work to limit the force amplifier if a voltage or current at the dut exceeds the set levels. the clamps also protect the dut if a transient voltage or current spike occurs when changing to a different operating mode or when programming the device to a different current range. the voltage clamps are available while forcing current, and the current clamps are available while forcing voltage. the user can set up the voltage or current clamp status (enabled or disabled) using the serial interface (system control register or pmu register). each clamp has a smooth, finite transition region between normal (unclamped) operation and the final clamped level, and an internal flag is activated within this transition zone. the open-drain cgalm pin indicates whether one or more pmu channels has clamped. the clamp status of an individual pmu can be determined by polling the alarm status register using the spi or lvds interface. cll should never be greater than clh. for the voltage clamps, there should be 500 mv between the cll and clh levels to ensure that a region exists in the middle of the clamps where both are off. similarly, set current clamps 250 mv away from 0 a. the transfer function for voltage clamping in fi mode is vcll or vclh = 4.5 vref ( dac_code /2 16 ) ? (3.5 vref ( offset_dac_code /2 16 )) + dutgnd see the dac levels section for more information. the transfer function for current clamping in fv mode is icll or iclh = 4.5 vref (( dac_code ? 32,768)/2 16 )/( r sense mi_amplifier_gain ) where: r sense is the sense resistor of the selected current range. mi_amplifier_gain is the gain of the measure current instrumentation amplifier, either 5 or 10. do not change clamp levels while the channel is in force mode because this can affect the forced voltage or current applied to the dut. similarly, the clamps should not be enabled or disabled during a force operation.
ad5522 rev. d | page 31 of 64 when the ad5522 is placed in high-z mode, the clamp circuit is always configured to monitor the measure current signal (irrespective of which high-z mode is selected, high-z v or high-z i). at this time, the clamp circuit is also comparing to the voltage clamp levels. because the device is in high-z mode, the measure current signal is at zero, but zero for the measure current is always the vmid voltage set by the offset dac. for default offset dac conditions, this causes no concern. for other settings of the offset dac, the zero point follows the vmid, and as the clamp circuit is comparing the voltage clamp levels to the measure current signal, there may be instances where the voltage clamp levels cause the alarm to flag during high-z mode. to avoid this, the clamps can be disabled when going into high-z mode. current range selection integrated thin film resistors minimize the need for external components and allow easy selection of any of these current ranges: 5 a (200 k), 20 a (50 k), 200 a (5 k), and 2 ma (500 ). one current range up to 80 ma can be accommodated per channel by connecting an external sense resistor. for current ranges in excess of 80 ma, it is necessary that an external amplifier be used. for the suggested current ranges, the maximum voltage drop across the sense resistors is 1 v. however, to allow for error correction, there is some overrange available in the current ranges (12.5% or 0.125 v across r sense ). the full-scale voltage range that can be loaded to the fin dac is 11.5 v; the forced current can be calculated as follows: fi = 4.5 vref (( dac_code ? 32,768)/2 16 )/( r sense mi_amplifier_gain ) where: fi is the forced current. r sense is the selected sense resistor. mi_amplifier_gain is the gain of the measure current instrumentation amplifier. this gain can be set to 5 or 10 via the serial interface. in the 200 a range with the 5 k sense resistor and an i sense gain of 10, the maximum current range possible is 225 a. similarly, for the other current ranges, there is an overrange of 12.5% to allow for error correction. also, the forced current range is the quoted full-scale range only with an applied reference of 5 v or 2.5 v (with i sense amplifier gain = 5). the i sense amplifier is biased by the vmid dac voltage in such a way as to center the measure current output irrespective of the voltage span used. when using the extfohx outputs for current ranges up to 80 ma, there is no switch in series with the extfohx line, ensuring minimum capacitance present at the output of the force amplifier. this feature is important when using a pin electronics driver to provide high current ranges. high current ranges with the use of an external high current amplifier, one high current range in excess of 80 ma is possible. the high current amplifier buffers the force output and provides the drive for the required current. to eliminate any timing concerns when switching between the internal ranges and the external high current range, there is a mode where the internal 80 ma stage can be enabled at all times. see table 26 for more information. dutgnd measvhx dut r sense r sense extmeasihx extmeasilx fohx extfohx high current amplifier cffx fin internal range select (5a, 20a, 200a, 2ma) dac ? ? ? ? ? ? + + + ? + + + + 5 or 10 1 agnd measoutx 1 or 0.2 4k ? 2k? vmid to center i range 4k ? en 06197-028 figure 47. addition of high current amplifier for wider current range (>80 ma)
ad5522 rev. d | page 32 of 64 measure current gains t he measure current amplifier has two gain settings, 5 and 10. the two gain settings allow users to achieve the quoted/specified current ranges with large or small voltage swing. use the 10 gain setting with a 5 v reference, and use the 5 gain setting with a 2.5 v reference. both combinations ensure the specified current ranges. using other vref/gain setting combinations should achieve smaller current ranges only. achieving greater current ranges than the specified ranges is outside the intended opera- tion of the ad5522. the maximum guaranteed voltage across r sense = 1.125 v. f ollowing are examples of vref/gain setting combinations. in these examples, the offset dac is at its default value of 0xa492. ? vref = 5 v results in a 11.25 v range. using a gain setting of 10, there is 1.125 v maximum across r sense , resulting in current ranges of 5.625 a, 22.5 a, and so on (inclu- ding overrange of 12.5% to allow for error correction). ? vref = 2.5 v results in a 5.625 v range. using a gain setting of 5 results in current ranges of 5.625 a, 22.5 a, and so on (including overrange of 12.5% to allow for error correction). vref = 3.5 v results in a 7.87 v range. using a gain setting of 10, there is 0.785 v maximum across r sense , resulting in current ranges of 3.92 a, 15.74 a, and so on (including overrange of 12.5% to allow for error correction). vmid voltage the midcode voltage (vmid) is used in the measure current amplifier block to center the current ranges about 0 a. this is required to ensure that the quoted current ranges can be achieved when using offset dac settings other than the default. vmid corresponds to 0x8000 or the dac midcode value, that is, the middle of the voltage range set by the offset dac setting (see table 13 ). see the block diagram in figure 48 . vmid = 4.5 vref (32,768/2 16 ) ? (3.5 vref ( offset_dac_code /2 16 )) or vmid = 3.5 vref ((42,130 ? offset_dac_code )/2 16 ) vmin = ?3.5 vref ( offset_dac_code /2 16 ) vref vtop vmid vdac_mid voffset dac hv amp sel10 sel10 measvhx dutgnd int/extmeasihx measure current in-amp measure voltage in-amp int/extmeasilx 06197-043 sel5 1r 1r 1r 1r 1r 1r 10r 10r 1r 1r att r agnd sel5 5r 5r 5r 2r 7r 2r 7r voffset dac hv amp agnd at tb attb refgnd measoutx att = attenuation for measoutx 0.2 mi = measure current mv = measure voltage sel5 = mi gain = 5 sel10 = mi gain = 10 at tb att mi mv inamp10 inamp1 vmin vdac_min data address dac 50 ? figure 48. measure block and vmid influence
ad5522 rev. d | page 33 of 64 choosing power supply rails as noted in the specifications section, the minimum supply variation across the part |avdd ? avss| 20 v. for the ad5522 circuits to operate correctly, the supply rails must take into account not only the force voltage range, but also the internal dac minimum voltage level, as well as headroom and so on. the dac amplifier gains vref by 4.5, and the offset dac centers that range about some chosen point. the supplies need to cater to the dac output voltage range to avoid impinging on other parts of the circuit (for example, if the measure current block for rated current ranges has a gain of 10/5, the supplies need to provide sufficient headroom and footroom to not clip the measure current circuit when full current range is required). also, the measout gain = 0.2 setting uses the vmin level for scaling purposes; if there is not enough footroom for this vmin level, then the mv and mi output voltage range is affected. for the measout gain = 0.2 setting, it is important to choose avss based on the following: avss ?3.5 ( vref ( offset_dac_code /2 16 )) ? avss_footroom ? v dutgnd ? ( r cable i load ) where: avss_footroom = 4 v. v dutgnd is the voltage range anticipated at dutgnd. r cable is the cable/path resistance. i load is the maximum load current. measure output (measoutx pins) the measured dut voltage or current (voltage representation of dut current) is available on the measoutx pin with respect to agnd. the default measoutx range is the forced voltage range for voltage measure and current measure (nominally 11.25 v, depending on the reference voltage and offset dac) and includes some overrange to allow for offset correction. the serial interface allows the user to select another measoutx range of 0.9 vref to agnd, allowing an adc with a 5 v input range to be used. the measoutx line for each pmu channel can be made high impedance via the serial interface. the offset dac directly offsets the measured output voltage level, but only when gain1 = 0. when the measout gain is 0.2, the minimum code from the dac is used to center the measoutx voltage and to ensure that the voltage is within the range of 0 to 0.9 vref (see figure 48 ). when using low supply voltages, ensure that there is sufficient headroom and footroom for the dac output range (set by the vref and offset dac setting). device under test ground (dutgnd) by default, there is one dutgnd input available for all four pmu channels. however, in some pmu applications, it is necessary that each channel operate from its own dutgnd level. the dual function pin, guardinx/dutgndx, can be configured as an input to the guard amplifier (guardin) or as a dutgnd input for each channel. the pin function can be configured through the serial interface on power-on for the required operation. the default connection is sw13b (guardin) and sw14b (shared dutgnd). table 10. measoutx output ranges for gain1 = 0, measout gain = 1 output voltage range for vref = 5 v 1 measout function measure current gain transfer function offset dac = 0x0 offset dac = 0xa492 offset dac = 0xed67 mv 5 or 10 v dut 0 v to 22.5 v 11.25 v ?16.26 v to +6.25 v mi gain0 = 0 10 (i dut r sense 10) + vmid 0 v to 22.5 v 11.25 v ?16.26 v to +6.25 v gain0 = 1 5 (i dut r sense 5) + vmid 0 v to 11.25 v (vref = 2.5 v) 5.625 v (vref = 2.5 v) ?8.13 v to +3.12 v (vref = 2.5 v) 1 vref = 5 v unless otherwise noted. table 11. measoutx output ranges for gain1 = 1, measout gain = 0.2 measout function measure current gain transfer function output voltage range for vref = 5 v 1 , 2 mv 5 or 10 v dut 0.2 + (0.45 vref) 0 v to 4.5 v (2.25 v centered around 2.25 v) mi gain0 = 0 10 (i dut r sense 10 0.2) + (0.45 vref) 0 v to 4.5 v (2.25 v centered around 2.25 v) gain0 = 1 5 (i dut r sense 5 0.2) + (0.45 vref) 1.125 v to 3.375 v (1.125 v, centered around 2.25 v) 0 v to 2.25 v (1.125 v, centered around 1.125 v) (vref = 2.5 v) 1 vref = 5 v unless otherwise noted. 2 the offset dac setting has no effect on the output voltage range.
ad5522 rev. d | page 34 of 64 when configured as dutgnd per channel, this dual function pin is no longer connected to the input of the guard amplifier. instead, it is connected to the low end of the instrumentation amplifier (sw14a), and the input of the guard amplifier is connected internally to measvhx (sw13a). dutgnd measure voltage in-amp measvh[0:3] guard[0:3] guardin[0:3]/ dutgnd[0:3] dut guard amp sw14 sw13 sw16 b b a a ? ? ? + + + x1 agnd 06197-029 figure 49. using the dutgnd per channel feature guard amplifier a guard amplifier allows the user to bootstrap the shield of the cable to the voltage applied to the dut, ensuring minimal drops across the cable. this is particularly important for measurements requiring a high degree of accuracy and in leakage current testing. if not required, all four guard amplifiers can be disabled via the serial interface (system control register). disabling the guard amplifiers decreases power consumption by 400 a per channel. as described in the device under test ground (dutgnd) section, guardinx/dutgndx are dual function pins. each pin can function either as a guard amplifier input for one chan- nel or as a dutgnd input for one channel, depending on the requirements of the end application (see figure 49 ). a guard alarm event occurs when the guard output moves more than 100 mv away from the guard input voltage for more than 200 s. in this case, the event is flagged via the open-drain output cgalm . because the guard and clamp alarm functions share the same alarm output, cgalm , the alarm information (alarm trigger and alarm channel) is available via the serial interface in the alarm status register. alternatively, the serial interface allows the user to set up the cgalm output to flag either the clamp status or the guard status. by default, this open-drain alarm pin is an unlatched output, but it can be configured as a latched output via the serial interface (system control register). compensation capacitors each channel requires an external compensation capacitor (ccomp) to ensure stability into the maximum load capacitance while ensuring that settling time is optimized. in addition, one cff pin per channel is provided to further optimize stability and settling time performance when in force voltage (fv) mode. when changing from force current (fi) mode to fv mode, the internal switch connecting the cff capacitor is automatically closed. although the force amplifier is designed to drive load capacitances up to 10 nf (with ccomp capacitor = 100 pf), it is possible to use larger compensation capacitor values to drive larger loads, at the expense of an increase in settling time. if a wide range of load capacitances must be driven, an external multiplexer connected to the ccompx pin allows optimization of settling time vs. stability. the series resistance of a switch placed on ccompx should typically be <50 . suitable multiplexers for use are the adg1404 , adg1408 , or one of the multiplexers in the adg4xx family, which typically have on resistances of less than 50 . similarly, connecting the cff node to an external multiplexer accommodates a wide range of c dut in fv mode. the adg1204 or adg1209 family of multiplexers meet these requirements. the series resistance of the multiplexer used should be such that 1/(2 r on c dut ) > 100 khz the voltage range of the cffx and ccompx pins is the same as the voltage range expected on the fohx pin; therefore, choice of capacitor must take this into account. table 12. suggested compensation capacitor selection c load ccomp capacitor cff capacitor 1 nf 100 pf 220 pf 10 nf 100 pf 1 nf 100 nf c load /100 c load /10
ad5522 rev. d | page 35 of 64 temperature sensor system force and sense switches an on-board temperature sensor monitors die temperature. the temperature sensor is located at the center of the die. if the temperature exceeds the factory specified value (130c) or a user programmable value, the device protects itself by shutting down all channels and flagging an alarm through the latched, open-drain tmpalm pin. alarm status can be read back from the alarm status register or the pmu register, where latched and unlatched bits indicate whether an alarm has occurred and whether the temperature has dropped below the set alarm temperature. the shutdown temperature is set using the system control register. each channel has switches to allow connection of the force (fohx) and sense (measvhx) lines to a central pmu for calibration purposes. there is one set of sys_force and sys_sense pins per device. it is recommended that these connections be made individually to each pmu channel. foh0 foh1 foh2 foh3 sys_force 06197-042 measvh0 measvh1 measvh2 measvh3 sys_sense figure 50. sys_force and sys_sense connections to fohx and measvhx pins
ad5522 rev. d | page 36 of 64 dac levels each channel contains five dedicated dac levels: one for the force amplifier, one each for the clamp high and clamp low levels, and one each for the comparator high and comparator low levels. the architecture of a single dac channel consists of a 16-bit resistor-string dac followed by an output buffer amplifier. this resistor-string architecture guarantees dac monotonicity. the 16-bit binary digital code loaded to the dac register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. the transfer function for dac outputs is as follows: vout = 4.5 vref ( x2 /2 16 ) ? (3.5 vref ( offset_dac_code /2 16 )) + dutgnd where: vref is the reference voltage and is in the range of 2 v to 5 v. x2 is the calculated dac code value and is in the range of 0 to 65,535 (see the gain and offset registers section). offset_dac_ code is the code loaded to the offset dac. it is multiplied by 3.5 in the transfer function. on power-up, the default code loaded to the offset dac is 0xa492; with a 5 v reference, this gives a span of 11.25 v. offset dac the ad5522 is capable of forcing a 22.5 v (4.5 vref) voltage span. included on chip is one 16-bit offset dac (one for all four channels) that allows for adjustment of the voltage range. the usable range is ?16.25 v to +22.5 v. zero scale loaded to the offset dac gives a full-scale range of 0 v to 22.5 v, midscale gives 11.25 v, and the most useful negative range is ?16.25 v to +6.25 v. full scale loaded to the offset dac does not give a useful output voltage range, because the output amplifiers are limited by the available footroom. tabl e 13 shows the effect of the offset dac on the other dacs in the device. table 13. relationship of of fset dac to other dacs (vref = 5 v) offset dac code dac code dac output voltage (v) 0 0 0 32,768 +11.25 65,535 +22.50 32,768 0 ?8.75 32,768 +2.50 65,535 +13.75 42,130 0 ?11.25 32,768 0 65,535 +11.25 60,855 0 ?16.25 32,768 ?5.00 65,535 +6.25 65,535 footroom limitations the power supplies should be selected to support the required range and should take into account amplifier headroom and footroom and sense resistor voltage drop (4 v). therefore, depending on the headroom available, the input to the force amplifier can be unipolar positive or bipolar, either symmetrical or asymmetrical about dutgnd, but always within a voltage span of 22.5 v. the offset dac offsets all dac functions. it also centers the current range so that zero current always flows at midscale code, regardless of the offset dac setting. rearranging the transfer function for the dac output gives the following equation to determine which offset dac code is required for a given reference and output voltage range. offset_dac_code = (2 16 ( vout ? dutgnd ))/ (3.5 vref ) ? ((4.5 dac_code )/3.5) when the output range is adjusted by changing the default value of the offset dac, an extra offset is introduced due to the gain error of the offset dac channel. the amount of offset is depen- dent on the magnitude of the reference and how much the offset dac channel deviates from its default value. see the specifications section for this offset. the worst-case offset occurs when the offset dac channel is at positive or negative full scale. this value can be added to the offset present in the main dac channel to give an indication of the overall offset for that channel. in most cases, the offset can be removed by programming the c register of the channel with an appropriate value. the extra offset caused by the offset dac needs to be taken into account only when the offset dac is changed from its default value. gain and offset registers each dac level has an independent gain (m) register and an independent offset (c) register, which allow trimming out of the gain and offset errors of the entire signal chain, including the dac. all registers in the ad5522 are volatile, so they must be loaded on power-on during a calibration cycle. data from the x1 register is operated on by a digital multiplier and adder controlled by the contents of the m and c registers. the cali- brated dac data is then stored in the x2 register. the digital input transfer function for each dac can be represented as follows: x2 = [( m + 1)/2 n x1] + ( c ? 2 n ? 1 ) where: x2 is the data-word loaded to the resistor-string dac. x1 is the 16-bit data-word written to the dac input register. m is the code in the gain register (default code = 2 16 ? 1). the m register is 15 bits (d15 to d1, the lsb is a dont care). c is the code in the offset register (default code = 2 15 ). n is the dac resolution ( n = 16).
ad5522 rev. d | page 37 of 64 the calibration engine is engaged only when data is written to the x1 register and for some pmu writes (see table 18 ). the calibration engine is not engaged when data is written to the m or c register. this has the advantage of minimizing the initial setup time of the device. to calculate a result that includes new m or c data, a write to x1 is required. cached x2 registers each dac has a number of cached x2 registers. these registers store the result of a gain and offset calibration in advance of a mode change. this enables the user to preload registers, allowing the calibration engine to calculate the appropriate x2 value and store it until a change in mode occurs. because the data is ready and held in the appropriate register, mode changing is as time efficient as possible. if an update occurs to a dac register set that is currently part of the operating pmu mode, the dac output is updated immediately (depending on the load condition). gain and offset registers for the fin dac the force amplifier input (fin) dac level contains independent gain and offset control registers that allow the user to digitally trim gain and offset. there are six sets of x1, m, and c registers: one set for the force voltage range and one set for each force current range (four internal current ranges and one external current range). six x2 registers store the calculated dac values, ready to load to the dac register upon a pmu mode change. serial i/f fin 16 16 16 x1 reg creg mreg 6 16 16-bit fin dac offset d a c x2 reg vref 06197-030 figure 51. fin dac registers gain and offset registers for the comparator dacs the comparator dac levels contain independent gain and offset control registers that allow the user to digitally trim gain and offset. there are six sets of x1, m, and c registers: one set for the force voltage mode and one set for each force current range (four internal current ranges and one external current range). in this way, x2 can be preprogrammed, which allows for efficient switching into the required compare mode. six x2 registers store the calculated dac values, ready to load to the dac register upon a pmu mode change. serial i/f cpl 16 16 16 x1 reg creg mreg 6 16 16-bit cpl dac x2 reg vref cph 16 16 16 x1 reg creg mreg 6 16 16-bit cph dac x2 reg 06197-031 figure 52. comparator registers gain and offset registers for the clamp dacs the clamp dac levels contain independent gain and offset control registers that allow the user to digitally trim gain and offset. there are two sets of x1, m, and c registers: one set for the force voltage mode and one set for all five current ranges. two x2 registers store the calculated dac values, ready to load to the dac register upon a pmu mode change. serial i/f cll 16 16 16 x1 reg creg mreg 16 16-bit cll dac x2 reg v ref clh 16 16 16 x1 reg creg mreg 16 16-bit clh dac x2 reg 06197-032 2 2 figure 53. clamp registers reference voltage (vref) one buffered analog input, vref, supplies all 21 dacs with the necessary reference voltage to generate the required dc levels. reference selection the voltage applied to the vref pin determines the output voltage range and span applied to the force amplifier, clamp, and comparator inputs. the ad5522 can be used with a reference input ranging from 2 v to 5 v; however, for most applications, a reference input of 5 v or 2.5 v is sufficient to meet all voltage range requirements. the dac amplifier gain is 4.5, which gives a dac output span of 22.5 v. the dacs have gain and offset registers that can be used to trim out system errors. in addition, the gain register can be used to reduce the dac output range to the desired force voltage range. the fin dac retains 16-bit resolution even with a gain register setting of quarter scale (0x4000). therefore, from a single 5 v reference, it is possible to obtain a voltage span as high as 22.5 v or as low as 5.625 v. when using the gain and offset registers, the selected output range should take into account the system gain and offset errors that need to be trimmed out. therefore, the selected output range should be larger than the actual required range. when using low supply voltages, ensure that there is sufficient headroom and footroom for the required force voltage range. also, the forced current range is the quoted full-scale range only with an applied reference of 5 v (i sense amplifier gain = 10) or 2.5 v (i sense amplifier gain = 5).
ad5522 rev. d | page 38 of 64 table 14. references suggested for use with ad5522 1 part no. voltage (v) initial accuracy % ref out tc (ppm/c) ref output current (ma) supply voltage range (v) package adr435 5 0.04 1 30 +7 to +18 msop, soic adr445 5 0.04 1 10 +5.5 to +18 msop, soic adr431 2.5 0.04 1 30 +4.5 to +18 msop, soic adr441 2.5 0.04 1 10 +3 to +18 msop, soic 1 subset of the possible references suitable fo r use with the ad5522. visit www.analog.com for more options. fo r other voltage and current ranges, the required reference level can be calculated as follows: 1. identify the nominal range required. 2. identify the maximum offset span and the maximum gain required on the full output signal range. 3. calculate the new maximum output range, including the expected maximum gain and offset errors. 4. choose the new required vout max and vout min , keeping the vout limits centered on the nominal values. note that avdd and avs s must provid e suf f icient he a dro om. 5. calculate the value of vref as follows: vref = ( vout max ? vout min )/4.5 reference selection example if, given the following conditions: nominal output range = 10 v (?2 v to +8 v) offset error = 100 mv gain error = 0.5% refgnd = agnd = 0 v then, with gain error = 0.5%, the maximum positive gain error = +0.5%, and the output range including gain error = 10 v + 0.005(10 v) = 10.05 v. with offset error = 100 mv, the maximum offset error span = 2(100 mv) = 0.2 v, and the output range including gain error and offset error = 10.05 v + 0.2 v = 10.25 v. to calculate vref with actual output range = 10.25 v, that is, ?2.125 v to +8.125 v (centered), v ref = (8.125 v + 2.125 v)/4.5 = 2.28 v i f the solution yields an inconvenient reference level, the user can adopt one of the following approaches: ? use a resistor divider to divide down a convenient, higher reference level to the required level. ? select a convenient reference level above vref and modify the gain and offset registers to digitally downsize the reference. in this way, the user can use almost any convenient refer- ence level. ? use a combination of these two approaches. in this case, the optimum reference is a 2.5 v reference; the user can use the m and c registers and the offset dac to achieve the required ?2 v to +8 v range. change the i sense amplifier gain to 5 to ensure a full-scale current range of the specified values (see the current range selection section). this gain also allows opti- mization of power supplies and minimizes power consumption within the device. it is important to bear in mind when choosing a reference value that values other than 5 v (mi gain = 10) and 2.5 v (mi gain = 5) result in current ranges other than those specified. see the measure current gains section for more details. calibration calibration involves determining the gain and offset of each channel in each mode and overwriting the default values in the m and c registers of the individual dacs. in some cases (for example, fi mode), the calibration constants, particularly those for gains, may be range dependent. re ducing zero-scale error ze ro-scale error can be reduced as follows: 1. set the output to the lowest possible value. 2. measure the actual output voltage and compare it to the required value. this gives the zero-scale error. 3. calculate the number of lsbs equivalent to the zero-scale error and add/subtract this number to the default value of the c register. re ducing gain error ga in error can be reduced as follows: 1. measure the zero-scale error. 2. set the output to the highest possible value. 3. measure the actual output voltage and compare it to the required value. this is the gain error. 4. calculate the number of lsbs equivalent to the gain error and subtract this number from the default value of the m register. note that only positive gain error can be reduced.
ad5522 rev. d | page 39 of 64 calibration example nominal offset coefficient = 32,768 nominal gain coefficient = 65,535 for example, the gain error = 0.5%, and the offset error = 100 mv. gain error (0.5%) calibration: 65,535 0.995 = 65,207 therefore, load code 1111 1110 1011 0111 to the m register. offset error (100 mv) calibration: lsb size = 10.25/65,535 = 156 v offset coefficient for 100 mv offset = 100/0.156 = 641 lsbs therefore, load code 0111 1101 0111 1111 to the c register. additional calibration the techniques described in the calibration section are usually sufficient to reduce the zero-scale and gain errors. however, there are limitations whereby the errors may not be sufficiently reduced. for example, the offset (c) register can only be used to reduce the offset caused by negative zero-scale error. a positive offset cannot be reduced. likewise, if the maximum voltage is below the ideal value, that is, a negative gain error, the gain (m) register cannot be used to increase the gain to compensate for the error. these limitations can be overcome by increasing the reference value. system level calibration th ere are many ways to calibrate the device on power-on. following is an example of how to calibrate the fin dac of the device without a dut or dut board connected. the calibration procedure for the force and measure circuitry is as follows: 1. calibrate the force voltage (2 points). in fv mode, write zero scale to the fin dac. connect sys_force to fohx and sys_sense to measvhx, and close the internal force/sense switch (sw7). us ing the system pmu, measure the error between the voltage at fohx/measvhx and the desired value. similarly, load full scale to the fin dac and measure the error between the voltage at fohx/measvhx and the desired value. calculate the m and c values. load these values to the appropriate m and c registers of the fin dac. 2. calibrate the measure voltage (2 points). connect sys_force to fohx and sys_sense to measvhx, and close the internal force/sense switch (sw7). force voltage on fohx via sys_force and measure the voltage at measoutx. the difference is the error between the actual forced voltage and the voltage at measoutx. 3. calibrate the force current (2 points). in fi mode, write zero scale to the fin dac. connect sys_force to an external ammeter and to the fohx pin. measure the error between the ammeter reading and the measoutx reading. repeat this step with full scale loaded to the fin dac. calculate the m and c values. 4. calibrate the measure current (2 points). in fi mode, write zero scale to the fin dac. connect sys_force to an external ammeter and to the fohx pin. measure the error between the ammeter reading and the measoutx reading. repeat this step with full scale loaded to the fin dac. 5. repeat this procedure for all four channels. similarly, calibrate the comparator and clamp dacs, and load the appropriate gain and offset registers. calibrating these dacs requires some successive approximation to find where the comparator trips or the clamps engage.
ad5522 rev. d | page 40 of 64 circuit operation force voltage (fv) mode most pmu measurements are performed in force voltage/measure current (fvmi) mode, for example, when the device is used as a device power supply, or in continuity or leakage testing. in force voltage (fv) mode, the voltage forced is mapped directly to the dut. the measure voltage amplifier completes the loop, giving negative feedback to the forcing amplifier (see figure 54 ). the forced voltage can be calculated as follows: forced voltage at dut = vout vout = 4.5 vref ( dac_code /2 16 ) ? (3.5 vref ( offset_dac_code /2 16 )) + dutgnd where: vout is the voltage of the fin dac (see the dac levels section). dutgnd measvhx dut r sense (up to 80ma) r sense extmeasihx extmeasilx fohx extfohx cffx fin force amplifier internal range select (5a, 20a, 200a, 2ma) dac ? ? ? ? ? ? + + + ? + + + + 5 or 10 1 agnd measure voltage amplifier measoutx vmid to center i range 06197-033 1 or 0.2 4k ? 2k? 4k ?
ad5522 rev. d | page 41 of 64 force current (fi) mode in force current (fi) mode, the voltage at the fin dac is converted to a current and is applied to the dut. the feedback path is the measure current amplifier, feeding back the voltage measured across the sense resistor. measoutx reflects the voltage measured across the dut (see figure 55 ). for the suggested current ranges, the maximum voltage drop across the sense resistors is 1 v. however, to allow for error correction, there is some overrange available in the current ranges. the maximum full-scale voltage range that can be loaded to the fin dac is 11.5 v. the forced current can be calculated as follows: fi = 4.5 vref (( dac_code ? 32,768)/2 16 )/( r sense mi_amplifier_gain ) where: fi is the forced current. r sense is the selected sense resistor. mi_amplifier_gain is the gain of the measure current instrumentation amplifier. this gain can be set to 5 or 10 via the serial interface. the i sense amplifier is biased by the offset dac output voltage in such a way as to center the measure current output regardless of the voltage span used. in the 200 a range with the 5 k sense resistor and an i sense gain of 10, the maximum current range possible is 225 a. similarly, for the other current ranges, there is an overrange of 12.5% to allow for error correction. dutgnd dut r sense fin internal range select (5a, 20a, 200a, 2ma) dac ? ? ? ? ? ? + ? + + + + + + 5 or 10 1 agnd vmid to center i range 06197-034 r sense (up to 80ma) measvhx extmeasihx extmeasilx fohx extfohx cffx measoutx force amplifier measure current amplifier 1 or 0.2 4k ? 2k ? 4k ?
ad5522 rev. d | page 42 of 64 serial interface the ad5522 provides two high speed serial interfaces: an spi- compatible interface operating at clock frequencies up to 50 mhz and an eia-644-compliant lvds interface. to minimize both the power consumption of the device and the on-chip digital noise, the serial interface powers up fully only when the device is being written to, that is, on the falling edge of sync . spi interface the serial interface operates from a 2.3 v to 5.25 v dvcc supply range. the spi interface is selected when the spi /lvds pin is held low. it is controlled by four pins, as described in . table 15 table 15. pins that control the spi interface pin description sync frame synchronization input sdi serial data input pin sclk clocks data in and out of the device sdo serial data output pin fo r data readback (weak sdo output driver, may require reduction in sclk frequency to correctly read back, see table 2 ) lvds interface the lvds interface uses the same input pins, with the same designations, as the spi interface. in addition, four other pins are provided for the complementary signals needed for differ- ential operation, as described in table 16 . table 16. pins that control the lvds interface pin description sync differential frame synchronization signal sync differential frame synchronization signal (complement) sdi differential serial data input sdi differential serial da ta input (complement) sclk differential serial clock input sclk differential serial clock input (complement) sdo differential serial data output for data readback sdo differential serial data output for data readback (complement) serial interface write mode the ad5522 allows writing of data via the serial interface to every register directly accessible to the serial interface, that is, all registers except the dac registers. the serial word is 29 bits long. the serial interface works with both a continuous and a burst (gated) serial clock. serial data applied to sdi is clocked into the ad5522 by clock pulses applied to sclk. the first falling edge of sync starts the write cycle. at least 29 falling clock edges must be applied to sclk to clock in 29 bits of data before sync is taken high again. the input register addressed is updated on the rising edge of sync . for another serial transfer to take place, sync must be taken low again. the shift register can accept longer words (for example, 32-bit words), framed by sync , but the data should always be in the 29 th lsb positions. reset function bringing the level-sensitive reset line low resets the contents of all internal registers to their power-on reset state (see the section). this sequence takes approximately 600 s. power-on default busy goes low for the duration, returning high when reset is brought high again and the initialization is complete. while busy is low, all interfaces are disabled. when busy returns high, normal operation resumes, and the status of the reset pin is ignored until it goes low again. the sdo output is high impedance during a power-on reset or a reset . a power- on reset functions the same way as reset . busy and load functions the busy pin is an open-drain output that indicates the status of the ad5522 interface. when writing to any register, busy goes low and stays low until the command completes. a write operation to a dac x1 register and some pmu register bits (see table 1 8 ) drives the busy signal low for longer than a write m, c, or system control register. for dacs, the value of the internal cached (x2) data is calculated and stored each time that the user writes new data to the corresponding x1 register. during the calculation and writing of x2, the busy output is driven low. while busy is low, the user can continue writing new data to the any register, but this write should not be completed with sync going high until busy returns high (see and ). figure 56 figure 57 x2 values are stored and held until a pmu word is written that calls the appropriate cached x2 register. only then is a dac output updated. the dac outputs and pmu modes are updated by taking the load input low. if load goes low while busy is active, the load event is stored and the dac outputs or pmu modes are updated immediately after busy goes high. a user can also hold the load input permanently low. in this case, the dac outputs or pmu modes are updated immediately after busy goes high. the busy pin is bidirectional and has a 50 k internal pull-up resistor. when multiple ad5522 devices are used in one system, the busy pins can be tied together. this is useful when it is required that no dac or pmu in any device be updated until all others are ready to be updated. when each device finishes updating its x2 registers, it releases the busy pin. if another device has not finished updating its x2 registers, it holds busy low, thus delaying the effect of load going low.
ad5522 rev. d | page 43 of 64 because there is only one calibration engine shared among four channels, the task of calculating x2 values must be done sequentially, so that the length of the busy pulse varies according to the number of channels being updated. following any register update, including multiple channel updates, subsequent writes should either be timed or should wait until busy returns high (see figure 56). if subsequent writes are presented before the calibration engine completes the first stage of the last channel x2 calculation, data may be lost. table 17. a a busy e e aa pulse widths action busy pulse width 1 loading data to system control register, or readback 2 0.27 s maximum loading x1 to 1 pmu dac channel 1.65 s maximum loading x1 to 2 pmu dac channels 2.3 s maximum loading x1 to 3 pmu dac channels 2.95 s maximum loading x1 to 4 pmu dac channels 3.6 s maximum 1 busy pulse width = ((number of cha nnels + 1) 650 ns) + 350 ns. 2 refer to table 18 for details of pmu register effect on busy pulse width. busy also goes low during a power-on reset and when a falling edge is detected on the reset pin. write 1 first stage second stage third stage ~650ns 650ns 650ns calibr a tion engine time for example, write to 3 fin dac registers 350ns write 2 first stage second stage third stage first stage second stage third stage first stage second stage third stage 06197-035 figure 56. multiple writes to dac x1 registers writing data to the system control register, some pmu control bits (see table 18), the m register, and the c register do not involve the digital calibration engine, thus speeding up configuration of the device on power-on. however, care should be taken not to issue these commands while busy is low, as previously described. table 18. a a busy e e aa pulse widths for pmu register updates pmu register update (see table 26 ) maximum busy low time per channel update bit bit name one channel two channels three channels four channels 21 ch en 270 ns 20, 19 force1, force0 (depen ds on mode change) transition from transition to high-z fohx current (11) force current (01) 270 ns high-z fohx current (11) force volt age (00) 1.65 s 2.3 s 2.95 s 3.6 s high-z fohx current (11) high-z fohx voltage (10) 1.65 s 2. 3 us 2.95 us 3.6 s force current (01) high-z fohx current (11) 270 ns force current (01) high-z fohx volt age (10) 1.65 s 2.3 s 2.95 s 3.6 s force current (01) force voltage (00) 1.65 s 2.3 s 2.95 s 3.6 s high-z fohx voltage (10) force voltage (00) 270 ns high-z fohx voltage (10) force curre nt (01) 1.65 s 2.3 s 2.95 s 3.6 s high-z fohx voltage (10) high-z fohx current (11) 1.65 s 2. 3 s 2.95 s 3.6 s force voltage (00) high-z fohx voltage (10) 270 ns force voltage (00) high-z fohx cu rrent (11) 1.65 s 2. 3 s 2.95 s 3.6 s force voltage (00) force current (01) 1.65 s 2.3 s 2.95 s 3.6 s 17, 16, 15 c2 to c0; current range selection (a ny range change) 1.65 s 2.3 s 2.95 s 3.6 s 14, 13 measx (measure mode selection) 270 ns 12 fin 270 ns 11 sfo 270 ns 10 ss0 270 ns 9 cl 270 ns 8 cpolh 270 ns 7 compare v/i 1.65 s 2.3 s 2.95 s 3.6 s 6 clear 270 ns
ad5522 rev. d | page 44 of 64 register update rates the value of the x2 register is calculated each time the user writes new data to the corresponding x1 register and for some pmu register updates. the calculation is performed in a three-stage process. the first two stages take approximately 650 ns each, and the third stage takes approximately 350 ns. when the write to the x1 register is complete, the calculation process begins. if the write operation involves the update of a single dac channel, the user is free to write to another x1 register, provided that the write operation does not finish ( sync returns high) until after the first-stage calculation is complete, that is, 650 ns after the completion of the first write operation. write 1 write 2 write 3 first stage second stage third stage ~650ns 650ns 650ns calibr a tion engine time 350ns first stage second stage third stage first stage second stage third stage 06197-036 figure 57. multiple single-channel writ es engaging the calibration engine register selection the serial word assignment consists of 29 bits. bit 28 to bit 22 are common to all registers, whether writing to or reading from the device. the pmu3 to pmu0 data bits (bit 27 to bit 24) address each pmu channel (or associated dac register). when the pmu3 to pmu0 bits are all 0s, the system control register is addressed. the mode bits, mode0 and mode1, address the different sets of dac registers and the pmu register. table 19. mode bits b23 mode1 b22 mode0 action 0 0 write to the system control register or the pmu register 0 1 write to the dac gain (m) register 1 0 write to the dac offset (c) register 1 1 write to the dac input data (x1) register readback control, rd/ wr setting the rd/ wr bit (bit 28) high initiates a readback sequence of the pmu, alarm status, comparator status, system control, or dac register, as determined by the address bits. pmu address bits: pmu3, pmu2, pmu1, pmu0 the pmu3 to pmu0 data bits (bit 27 to bit 24) address each pmu channel on chip. these bits allow individual control of each pmu channel or any combination of channels, in addition to multichannel programming. pmu bits also allow access to write registers such as the system control register and the dac registers, in addition to reading from all the registers (see table 20 ). nop (no operation) if an nop (no operation) command is loaded, no change is made to the dac or pmu registers. this code is useful when performing a readback of a register within the device (via the sdo pin) where a change of dac code or pmu function may not be required. reserved commands any bit combination that is not described in the register address tables for the pmu, dac, and system control registers indicates a reserved command. these commands are unassigned and are reserved for factory use. to ensure correct operation of the device, do not use reserved commands.
ad5522 rev. d | page 45 of 64 all codes not explicitly referenced in this table are reserved and should not be used (see table 29 ). table 20. read and write functions of the ad5522 b28 b27 b26 b25 b24 b23 b22 b21 to b0 selected channel rd/ wr pmu3 pmu2 pmu1 pmu0 mode1 mode0 data bits ch3 ch2 ch1 ch0 write functions 0 0 0 0 0 0 0 data bits write to system control register (see table 23 ) 0 0 0 0 0 0 1 data bits reserved 0 0 0 0 0 1 0 data bits reserved 0 0 0 0 0 1 1 all 1s nop (no operation) 0 0 0 0 0 1 1 data bits other than all 1s reserved write addressed dac or pmu register 0 0 0 0 1 address and data bits ch0 0 0 0 1 0 ch1 0 0 0 1 1 ch1 ch0 0 0 1 0 0 select dac or pmu register (see table 19 ) ch2 0 0 1 0 1 ch2 ch0 0 0 1 1 0 ch2 ch1 0 0 1 1 1 ch2 ch1 ch0 0 1 0 0 0 ch3 0 1 0 0 1 ch3 ch0 0 1 0 1 0 ch3 ch1 0 1 0 1 1 ch3 ch1 ch0 0 1 1 0 0 ch3 ch2 0 1 1 0 1 ch3 ch2 ch0 0 1 1 1 0 ch3 ch2 ch1 0 1 1 1 1 ch3 ch2 ch1 ch0 read functions 1 0 0 0 0 0 0 all 0s read from system control register 1 0 0 0 0 0 1 all 0s read from comparator status register 1 0 0 0 0 1 0 x (dont care) reserved 1 0 0 0 0 1 1 all 0s read from alarm status register read addressed dac or pmu register (only one pmu or dac register can be read at one time) 1 0 0 0 1 ch0 1 0 0 1 0 ch1 1 0 1 0 0 ch2 1 1 0 0 0 select pmu or dac register (see table 19 ) all 0s if reading pmu registers; dac address plus all 0s if reading a dac register dac address (see table 29 ) ch3
ad5522 rev. d | page 46 of 64 write system control register the system control register is accessed when the pmu channel address bits (pmu3 to pmu0) and the mode bits (mode1 and mode0) are all 0s. this register allows quick setup of various functions in the device. the system control register operates on a per-device basis. table 21. system control regist er bitsbit b28 to bit b15 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 rd/ wr pmu3 pmu2 pmu1 pmu0 mode1 mode0 cl3 cl2 cl1 cl0 cpolh3 cpolh2 cpolh1 table 22. system control register bitsbit b14 to bit b0 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 1 b0 1 cpolh0 cpbiasen dutgnd/ch guard alm clamp alm int10k guard en gain1 gain0 tmp enable tmp1 tmp0 latched 0 0 1 bit b1 and bit b0 are unused data bits. table 23. system control register functions bit bit name description 28 (msb) rd/ wr when low, a write function takes place to the selected register; setting the rd/ wr bit high initiates a readback sequence of the pmu, alarm status, comparator status, system control, or dac register, as determined by the address bits. 27 pmu3 set bit pmu3 to bit pmu0 to 0 to address the system control register. 26 pmu2 25 pmu1 24 pmu0 23 mode1 set the mode1 and mode0 bits to 0 to address the system control register. 22 mode0 system control register-specific bits 21 cl3 20 cl2 19 cl1 18 cl0 current or voltage clamp enable. bit cl3 to bit cl0 enable and disable the current or voltage clamp function per channel (0 = disable; 1 = enable). the clamp enable function is also available in the pmu register on a per- channel basis. this dual functionality allows flexible enabling or disabling of this function. when reading back information about the status of the clamp enable function , the data that was most recently written to the clamp register is available in the readback word from eith er the pmu register or the system control register. 17 cpolh3 16 cpolh2 15 cpolh1 14 cpolh0 comparator output enable. by default, the comparator outputs are high-z on power-on. a 1 in each bit position enables the comparator output for the selected channel. bit 13 (cpbiasen) must be enabled to power on the comparator functions. the comparator enable function is also available in the pmu register on a per-channel basis. this dual functionality allows flexible enabling or disabling of this function. when reading back information about the status of the comparator enable function, the data that was most recently written to the comparator status register is available in the readback word from either the pmu register or the system control register. 13 cpbiasen comparator enable. by default, the comparators are powered down when the device is powered on. to enable the comparator function for all channels, write a 1 to this bit. a 0 disables the comparators and shuts them down. the comparator output enable bits (cpolhx, bit 17 to bit 14) allow th e user to turn on each comparator output individually, enabling busing of comparator outputs. 12 dutgnd/ch dutgnd per channel enable. the guardinx/dutgndx pins are shared pins that can be configured to enable a dutgnd per pmu channel or a guard input per pmu ch annel. setting this bit to 1 enables dutgnd per channel. in this mode, the pin functions as a dutgnd pin on a per-channel basis. the guard inputs are disconnected from this pin and instead are connected dire ctly to the measvhx line by an internal connection. the default power-on condition is guardinx. 11 guard alm 10 clamp alm clamp and guard alarm functions share one open-drain alarm pin ( cgalm ). by default, the cgalm pin is disabled. the guard alm and clamp alm bits allow the us er to choose whether clamp alarm information, guard alarm information, or both sets of alarm information are flagged by the cgalm pin. set high to enable either alarm function. 9 int10k internal sense short. setting this bit high allows the user to connect an in ternal sense short resistor of 10 k (4 k + 2 k switch + 4 k) between the fohx and the meas vhx lines (sw7 is closed). setting this bit high also closes sw15, allowing the user to connect another 10 k resistor between dutgndx and agnd. 8 guard en guard enable. the guard amplifier is disabled on power-on; to enable the guard amplifier, set this bit to 1. if the guard function is not in use, disabling it saves power (typically 400 a per channel).
ad5522 rev. d | page 47 of 64 bit bit name description 7 gain1 6 gain0 measoutx output range. the measoutx range defaults to the force voltage span for voltage and current measurements, which includes some overrange to allow for offset correction. the nominal output voltage range is 11.25 v with the default offset dac setting, but chan ges for other offset dac settings when gain1 = 0. therefore, the measoutx range can be an asymmetrical bipolar voltage range. gain1 = 1 enables a unipolar output voltage range, which allows the use of asymme trical supplies or a smaller input range adc. see table 10 and table 11 for more details. output voltage range for vref = 5 v, offset dac = 0xa492 measout function measure current gain gain1 = 0, measout gain = 1 gain1 = 1, measout gain = 0.2 mv 5 or 10 v dut (up to 11.25 v) 0 v to 4.5 v mi (gain0 = 0) 10 i dut r rsense 10 + vmid (up to 11.25 v) 0 v to 4.5 v mi (gain0 = 1) 5 i dut r rsense 5 + vmid (up to 5.625 v) 0 v to 2.25 v 5 tmp enable thermal shutdown feature. to disable the thermal shut down feature, set the tmp enable bit to 0 (thermal shutdown is enabled by default). 4 tmp1 the tmp1 and tmp0 bits allow the user to pr ogram the temperature that triggers thermal shutdown. 3 tmp0 tmp enable tmp1 tmp0 action 0 x x thermal shutdown disabled. 1 x x thermal shutdown enabled. 1 0 0 shutdown at junction temp erature of 130c (power-on default). 1 0 1 shutdown at junction temperature of 120c. 1 1 0 shutdown at junction temperature of 110c. 1 1 1 shutdown at junction temperature of 100c. 2 latched configure the open-drain pin ( cgalm ) as a latched or unlatched output pin. when high, this bit configures the cgalm alarm output as a latched output, allowing it to dr ive a controller i/o without needing to poll the line constantly. the power-on default for this pin is unlatched. 1 0 unused bits. set to 0. 0 (lsb) 0
ad5522 rev. d | page 48 of 64 write pmu register to address pmu functions, set the mode1 and mode0 bits to 0. this setting selects the pmu register (see table 19 and table 20 ). the ad5522 has very flexible addressing, which allows writing of data to a single pmu channel, any combination of pmu channels, or all pmu channels. this functionality enables multipin broadcasting to similar pins on a dut. bit 27 to bit 24 select the pmu or group of pmus that is addressed. table 24. pmu register bitsbit b28 to bit b15 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 1 b17 b16 b15 rd/ wr pmu3 pmu2 pmu1 pmu0 mode1 mode0 ch en force1 force0 0 c2 c1 c0 1 bit b18 is reserved. table 25. pmu register bitsbit b14 to bit b0 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 1 b4 1 b3 1 b2 1 b1 1 b0 1 meas1 meas0 fin sf0 ss0 cl cpolh compare v/i clear 0 0 0 0 0 0 1 bit b5 to bit b0 are unused data bits. table 26. pmu register functions bit bit name description 28 (msb) rd/ wr when low, a write to the selected register takes place; setting the rd/ wr bit high initiates a readback sequence of the pmu, alarm status, comparator status, system control, or dac register, as determined by the address bits. 27 pmu3 26 pmu2 25 pmu1 bit pmu3 to bit pmu0 address each pmu channel in the device. these bits allow control of an individual pmu channel or any combination of channels, in addition to multichannel programming (see table 20 ). 24 pmu0 23 mode1 22 mode0 set the mode1 and mode0 bits to 0 to access the pmu regist er selected by the pmu3 to pmu0 bits (bit 27 to bit 24). pmu register-specific bits 21 ch en channel enable. set high to enable the selected channel or group of channels; set low to disable the selected channel or channels. when disabled, sw2 is closed and sw5 is open (outputs are high-z). the measure mode is determined by the meas1 and meas0 bits at all times and is not affected by the ch en bit. the guard amplifier and the comparators are not affected by this bit. 20 force1 19 force0 the force1 and force0 bits set the force function for each pmu channel (in association with the pmux bits). all combinations of forcing and measuring (using the m eas1 and meas0 bits) are available. the high-z (voltage and current) modes allow the user to optimize glitch respon se during mode changes. while in high-z voltage or current mode, with the pmu high-z, new x1 codes loaded to the fin dac register and to the clamp dac register are calibrated, stored in the x2 register , and loaded directly to the dac outputs. force1 force0 action 0 0 fv and current clamp (if clamp is enabled). 0 1 fi and voltage clamp (if clamp is enabled). 1 0 high-z fohx voltage (preload fin dac and clamp dac). 1 1 high-z fohx current (preload fin dac and clamp dac). 18 reserved 0 17 c2 16 c1 bit c2 to bit c0 specify the required current range. high-z fv/fi commands ignore the current range address bits (c2, c1, and c0); therefore, these bit combinations cannot be used to enable or disable the force function for a pmu channel. c2 c1 c0 selected current range 0 0 0 5 a current range. 0 0 1 20 a current range. 0 1 0 200 a current range. 0 1 1 2 ma current range (default). 1 0 0 external current range. 1 0 1 disable the always on mode for the external current range buffer 1 . 1 1 0 enable the always on mode for the external current range buffer 2 . 15 c0 1 1 1 reserved.
ad5522 rev. d | page 49 of 64 bit bit name description 14 meas1 13 meas0 the meas1 and meas0 bits specify the required measure mode, allowing the measoutx line to be disabled, connected to the temperature sensor, or enabled for measurement of current or voltage. meas1 meas0 action 0 0 measoutx is connected to i sense 0 1 measoutx is connected to v sense 1 0 measoutx is connected to the temperature sensor 1 1 measoutx is high-z (sw12 open) 12 fin this bit sets the status of the force input (fin) amplifier. 0 = input of the force amplifier switched to gnd. 1 = input of the force amplifier connected to the fin dac output. 11 sf0 10 ss0 the sf0 and ss0 bits specify the switching of system force and sense lines to the force and sense paths at the dut. the channel to which the system force and system sense lines are connected is set by the pmu3 to pmu0 bits. for correct operation, only one pmu channel should be connected to the sys_force and sys_sense paths at any one time. sf0 ss0 action 0 0 sys_force and sys_sense are high-z for the selected channel 0 1 sys_force is high-z and sys_sense is connected to measvhx for the selected channels 1 0 sys_force is connected to fohx and sys_sense is high-z for the selected channel 1 1 sys_force is connected to fohx and sys_sense is connected to measvhx for the selected channel 9 cl per-pmu current or voltage clamp enable bit. a logic high enables the clamp function for the selected pmu. the clamp enable function is also available in the system co ntrol register. this dual functionality allows flexible enabling or disabling of this function. when reading back information about the status of the clamp enable function on a per-channel basis, the data that was most re cently written to the clamp register is available in the readback word from either the pmu register or the system control register. 8 cpolh comparator output enable bit. by defa ult, the comparator outputs are high-z on power-on. a logic high enables the comparator output for the selected pmu. the comparat or function cpbiasen (bit 13 in the system control register), must be enabled. the comparator output enable fu nction is also available in the system control register. this dual functionality allows flexible enabling or disabling of this function. when reading back information about the status of the comparator enable function, the data th at was most recently written to the comparator status register is available in the readback word from eith er the pmu register or the system control register. 7 compare v/i a logic high selects the compare voltage function; a logic low selects the compare current function. 6 clear to clear or reset a latched alarm bit and pin (temperature, gu ard, or clamp), write a 1 to this bit. this bit applies to latched alarm conditions (clamp and guard) on all four pmu channels. 5 unused unused bits. set to 0. 4 3 2 1 0 (lsb) 1 writing 101 in bit 17 to bit 15 disables the always on mode for the ex ternal current range buffer. use with fv mode (force1 = f orce0 = 0) only. to complete the disabling of the always on mode, the pmu ch annel is placed into high-z mode and the external current range buffer is returned t o its default operation (off). 2 writing 110 in bit 17 to bit 15 places the external current ra nge buffer into always on mode. in this mode, the buffer is alwa ys active with no regard to the selected current range. the always on mode is intended for use where an external high current stage is being used for a current drive in excess of 80 ma; having the internal stage always on should help to elimin ate timing concerns when transi tioning between this current range and other ranges. when first e nabling the always on mode, use it in conjunction with fv mode (force1 = force0 = 0); the device now enables the external current range bu ffer. the 110 code also pla ces the device into high-z mode (necessary to complete the enabling function). to return to an fv or fi operating mode, select the appropriate mode and current range. the external range sense resistor is connected to an mi circuit only when the external current range address is selected (c2 to c0 are set to 100). the default operation at power-on is disabled (or off).
ad5522 rev. d | page 50 of 64 write dac register the dac input, gain, and offset registers are addressed through a combination of pmu bits (bit 27 to bit 24) and mode bits (bit 23 and bit 22). bit a5 to bit a0 address each dac level on chip. bit d15 to bit d0 are the dac data bits used when writing to these registers. the pmu address bits allow addressing of a particular dac for any combination of pmu channels. table 27. dac register bits b28 b27 b26 b25 b24 b 23 b22 b21 b20 b19 b18 b17 b16 b15 to b0 rd/ wr pmu3 pmu2 pmu1 pmu0 mode1 mode0 a5 a4 a3 a2 a1 a0 data bits[d15 (msb):d0 (lsb)] table 28. dac register functions bit bit name description 28 (msb) rd/ wr when this bit is low, a write function takes place to the selected register; setting the rd/ wr bit high initiates a readback sequence of the pmu, alarm status, comparator status, system control, or dac register, as determined by the address bits. 27 pmu3 26 pmu2 25 pmu1 24 pmu0 bit pmu3 to bit pmu0 address each pmu and dac channel in the device. these bits allow control of each individual dac channel or any combination of channels, in addition to multichannel programming. 23 mode1 the mode1 and mode0 bits allow addressing of the dac gain (m), offset (c), or input (x1) register. 22 mode0 mode1 mode0 action 0 0 write to the system control register or the pmu register 0 1 write to the dac gain (m) register 1 0 write to the dac offset (c) register 1 1 write to the dac input data (x1) register dac register-specific bits 21 a5 dac address bits. the a5 to a3 bits select the register set that is addressed. see the dac addressing section. 20 a4 19 a3 18 a2 dac address bits. the a2 to a0 bits select the dac that is addressed. see the dac addressing section. 17 a1 16 a0 15 to 0 d15 (msb) to d0 (lsb) 16 dac data bits for x1 and c registers. m register is 15 bits wide, d15 to d1.
ad5522 rev. d | page 51 of 64 dac addressing for the fin and comparator (cph and cpl) dacs, there is a set of x1, m, and c registers for each current range, and one set for the voltage range; for the clamp dacs (cll and clh), there are only two sets of x1, m, and c registers. when calibrating the device, the m and c registers allow volatile storage of gain and offset coefficients. calculation of the corres- ponding dac x2 register occurs only when the x1 data is loaded (no internal calculation occurs on m or c updates). there is one offset dac for all four channels in the device that is addressed using the pmux bits. the offset dac has only an input register associated with it; no m or c registers are asso- ciated with this dac. when writing to the offset dac, set the mode1 and mode0 bits high to address the dac input register (x1). t he same address table is also used for readback of a particular dac address. n ote that cll is clamp level low and clh is clamp level high. ? when forcing a voltage, the current clamps are engaged; therefore, both the cll current ranges register set and the clh current ranges register set are loaded to the clamp dacs. ? when forcing a current, the voltage clamps are engaged; therefore, both the cll voltage range register set and the clh voltage range register set are loaded to the clamp dacs. all codes not explicitly referenced table 29 are reserved and should not be used. table 29. dac register addressing a5 a4 a3 a2 a1 a0 mode1 mode0 register set addressed register 0 0 0 0 0 0 1 1 n/a offset dac x 0 0 1 0 0 0 0 1 5 a current range fin m 1 0 fin c 1 1 fin x1 0 1 20 a current range fin m 1 0 fin c 0 0 1 0 0 1 1 1 fin x1 0 1 200 a current range fin m 1 0 fin c 0 0 1 0 1 0 1 1 fin x1 0 1 2 ma current range fin m 1 0 fin c 0 0 1 0 1 1 1 1 fin x1 0 1 external current range fin m 1 0 fin c 0 0 1 1 0 0 1 1 fin x1 0 1 voltage range fin m 1 0 fin c 0 0 1 1 0 1 1 1 fin x1 0 1 current ranges cll m 1 0 cll c 0 1 0 1 0 0 1 1 cll x1 1 0 1 voltage range cll m 1 0 cll c 0 1 0 1 0 1 1 1 cll x1 0 1 current ranges clh m 1 0 clh c 0 1 1 1 0 0 1 1 clh x1 2 0 1 voltage range clh m 1 0 clh c 0 1 1 1 0 1 1 1 clh x1 0 1 5 a current range cpl m 1 0 cpl c 1 0 0 0 0 0 1 1 cpl x1
ad5522 rev. d | page 52 of 64 a5 a4 a3 a2 a1 a0 mode1 mode0 register set addressed register 0 1 20 a current range cpl m 1 0 cpl c 1 0 0 0 0 1 1 1 cpl x1 0 1 200 a current range cpl m 1 0 cpl c 1 0 0 0 1 0 1 1 cpl x1 0 1 2 ma current range cpl m 1 0 cpl c 1 0 0 0 1 1 1 1 cpl x1 0 1 external current range cpl m 1 0 cpl c 1 0 0 1 0 0 1 1 cpl x1 0 1 voltage range cpl m 1 0 cpl c 1 0 0 1 0 1 1 1 cpl x1 0 1 5 a current range cph m 1 0 cph c 1 0 1 0 0 0 1 1 cph x1 0 1 20 a current range cph m 1 0 cph c 1 0 1 0 0 1 1 1 cph x1 0 1 200 a current range cph m 1 0 cph c 1 0 1 0 1 0 1 1 cph x1 0 1 2 ma current range cph m 1 0 cph c 1 0 1 0 1 1 1 1 cph x1 0 1 external current range cph m 1 0 cph c 1 0 1 1 0 0 1 1 cph x1 0 1 voltage range cph m 1 0 cph c 1 0 1 1 0 1 1 1 cph x1 1 cll should be within the range of 0x0000 to 0x7fff. 2 clh should be within the range of 0x8000 to 0xffff.
ad5522 rev. d | page 53 of 64 read registers readback of all the registers in the device is possible via the spi and the lvds interfaces. to read data from a register, it is first necessary to write a readback command to tell the device which register is required for readback. see table 30 to address the appropriate channel. when the required channel is addressed, the device loads the 24-bit readback data into the msb positions of the 29-bit serial shift register (the five lsbs are filled with 0s). sclk rising edges clock this readback data out on sdo (framed by the sync signal). a minimum of 24 clock rising edges is required to shift the readback data out of the shift register. if writing a 24-bit word to shift data out of the device, the user must ensure that the 24-bit write is effectively an nop (no operation) command. the last five bits in the shift register are always 00000: these five bits become the msbs of the shift register when the 24-bit write is loaded. to ensure that the device receives an nop command as described in table 20 , the recommended flush command is 0xffffff; thus, no change is made to any register in the device. readback data can also be shifted out by writing another 29-bit write or read command. if writing a 29-bit command, the read- back data is msb data available on sdo, followed by 00000. table 30. read functions of the ad5522 b28 b27 b26 b25 b24 b23 b22 b21 to b0 selected channel rd/ wr pmu3 pmu2 pmu1 pmu0 mode1 mode0 data bits ch3 ch2 ch1 ch0 read functions 1 0 0 0 0 0 0 all 0s read from system control register 1 0 0 0 0 0 1 all 0s read from comparator status register 1 0 0 0 0 1 0 x (dont care) reserved 1 0 0 0 0 1 1 all 0s read from alarm status register read addressed pmu register (only one pmu register can be read at one time) 1 0 0 0 1 0 0 all 0s ch0 1 0 0 1 0 0 0 ch1 1 0 1 0 0 0 0 ch2 1 1 0 0 0 0 0 ch3 read addressed dac m register (only one dac register can be read at one time) 1 0 0 0 1 0 1 ch0 1 0 0 1 0 0 1 ch1 1 0 1 0 0 0 1 ch2 1 1 0 0 0 0 1 dac address (see table 29 ) ch3 read addressed dac c register (only one dac register can be read at one time) 1 0 0 0 1 1 0 ch0 1 0 0 1 0 1 0 ch1 1 0 1 0 0 1 0 ch2 1 1 0 0 0 1 0 dac address (see table 29 ) ch3 read addressed dac x1 register (only one dac register can be read at one time) 1 0 0 0 1 1 1 ch0 1 0 0 1 0 1 1 ch1 1 0 1 0 0 1 1 ch2 1 1 0 0 0 1 1 dac address (see table 29 ) ch3
ad5522 rev. d | page 54 of 64 readback of system control register the system control register readback function is a 24-bit word. mode and system control register data bits are shown in table 3 1 . table 31. system control register readback bit bit name description 23 (msb) mode1 set the mode1 and mode0 bits to 0 to address the system control register. 22 mode0 system control register-specific readback bits 21 cl3 20 cl2 19 cl1 18 cl0 read back the status of the indivi dual current clamp enable bits. 0 = clamp is disabled. 1 = clamp is enabled. when reading back information about the status of the clamp enable function, the data that was most recently written to the current clamp register from ei ther the system control register or the pmu register is available in the readback word. 17 cpolh3 16 cpolh2 15 cpolh1 14 cpolh0 read back information about the status of the comparator output enable bits. 1 = pmu comparator output is enabled. 0 = pmu comparator output is disabled. when reading back information about the status of the comparator output enable function, the data that was most recently written to the comparator sta tus register from either the system control register or the pmu register is available in the readback word. 13 cpbiasen this readback bit indicates the status of the comparator enable function. 1 = comparator function is enabled. 0 = comparator function is disabled. 12 dutgnd/ch dutgnd per channel enable. 1 = dutgnd per channel is enabled. 0 = individual guard inputs are available per channel. 11 guard alm 10 clamp alm these bits provide information about which of these alarm bits trigger the cgalm pin. 1 = guard/clamp alarm is enabled. 0 = guard/clamp alarm is disabled. 9 int10k if this bit is high, the internal 10 k resistor (sw7) is connected between fohx and measvhx, and between dutgnd and agnd. if this bit is low, sw7 is open. 8 guard en read back the status of the guard amplifie rs. if this bit is high, the amplifiers are enabled. 7 gain1 status of the selected measoutx output range. see table 10 and table 11 . 6 gain0 5 tmp enable read back the status of the thermal shutdown function. 4 tmp1 bits[5:3] action 3 tmp0 0xx thermal shutdown disabled. 100 thermal shutdown enabled at junction temperature of 130c (power-on default). 101 thermal shutdown enabled at junction temperature of 120c. 110 thermal shutdown enabled at junction temperature of 110c. 111 thermal shutdown enabled at junction temperature of 100c. 1xx thermal shutdown enabled. 2 latched this bit indicates the status of the open-drain alarm outputs, tmpalm and cgalm . 1 = open-drain alarm outputs are latched. 0 = open-drain alarm outputs are unlatched. 1 0 (lsb) unused readback bits loads with 0s.
ad5522 rev. d | page 55 of 64 readback of pmu register the pmu register readback function is a 24-bit word that includes the mode and pmu data bits. only one pmu register can be read back at any one time. table 32. pmu register readback bit bit name description 23 (msb) mode1 set the mode1 and mode0 bits to 0 to access the selected pmu register. 22 mode0 pmu register-specific bits 21 ch en channel enable. if this bit is high, the selected channel is enabled; if this bit is low, the channel is disabled. 20 force1 19 force0 these bits indicate which force mode the selected channel is in. 00 = fv and current clamp (if clamp is enabled). 01 = fi and voltage clamp (if clamp is enabled). 10 = high-z fohx voltage. 11 = high-z fohx current. 18 reserved 0. 17 c2 16 c1 15 c0 these three bits indicate which forced or measured current range is set for the selected channel (see table 26 ). 14 meas1 13 meas0 these bits indicate which measure mode is selected : voltage, current, temperature sensor, or high-z. 00 = measoutx is connected to i sense . 01 = measoutx is connected to v sense . 10 = measoutx is connected to the temperature sensor. 11 = measoutx is high-z (sw12 open). 12 fin this bit shows the status of the force input (fin) amplifier. 0 = input of the force amplifier switched to gnd. 1 = input of the force amplifier connected to the fin dac output. 11 sf0 10 ss0 the system force and sense lines can be connected to any of the four pmu channels. these bits indicate whether the system force and sense lines are switched in (see table 26 ). 9 cl read back the status of the indivi dual current clamp enable bits. 1 = clamp is enabled on this channel. 0 = clamp is disabled on this channel. when reading back information about the status of the current clamp enable function, the data that was most recently written to the cu rrent clamp register from either the system control register or the pmu register is available in the readback word. 8 cpolh read back the status of the comparator output enable bit. 1 = pmu comparator output is enabled. 0 = pmu comparator output is disabled. when reading back information abo ut the status of the comparator output enable function, the data that was most recently written to the comparator register from either the system control register or the pmu register is available in the readback word. 7 compare v/i 1 = compare voltage function is enabled on the selected channel. 0 = compare current function is enabled on the selected channel. 6 ltmpalm 5 tmpalm tmpalm corresponds to the open-drain tmpalm output pin that flags a temperature event exceeding the default or user programmed level. the temper ature alarm is a per-device alarm; the latched ( ltmpalm ) and unlatched ( tmpalm ) bits indicate whether a temp erature event occurred and whether the alarm still exists (that is, whether the juncti on temperature still exceeds the programmed alarm level). to reset an alarm event, the user must write a 1 to the clear bit (bit 6) in the pmu register. 4 to 0 (lsb) unused readback bits loads with 0s.
ad5522 rev. d | page 56 of 64 readback of comparator status register the comparator status register is a read-only register that provides access to the output status of each comparator pin on the chip. table 33 shows the format of the comparator register readback word. readback of alarm status register the alarm status register is a read-only register that provides information about temperature, clamp, and guard alarm events (see table 34 ). temperature alarm status is also available in any of the four pmu readback registers. table 33. comparator status register (read-only) bit bit name description 23 (msb) mode1 0 22 mode0 1 comparator status register-specific bits 21 cpol0 20 cpoh0 19 cpol1 18 cpoh1 17 cpol2 16 cpoh2 15 cpol3 14 cpoh3 comparator output conditions per channel corr esponding to the comparator output pins. 1 = pmu comparator output is high. 0 = pmu comparator output is low. 13 to 0 (lsb) unused readback bits loads with zeros. table 34. alarm status register readback bit bit name description 23 (msb) mode1 1 22 mode0 1 alarm status register-specific bits 21 ltmpalm 20 tmpalm tmpalm corresponds to the open-drain tmpalm output pin that flags a temperature event exceeding the default or user programmed level. th e temperature alarm is a per-device alarm; the latched ( ltmpalm ) and unlatched ( tmpalm ) bits indicate whether a temperature event occurred and whether the alarm still exists (that is, whet her the junction temperature still exceeds the programmed alarm level). to reset an alarm event, th e user must write a 1 to the clear bit (bit 6) in the pmu register. 19 lg0 18 g0 17 lg1 16 g1 15 lg2 14 g2 13 lg3 12 g3 lgx is the per-channel latched guard alarm bit, and gx is the unlatched guard alarm bit. these bits indicate which channel flagged the alarm on the open-drain alarm pin, cgalm , and whether the alarm condition still exists. 11 lc0 10 c0 9 lc1 8 c1 7 lc2 6 c2 5 lc3 4 c3 lcx is the per-channel latched clamp alarm bit, and cx is the unlatched clamp alarm bit. these bits indicate which channel flagged the alarm on the open-drain alarm pin cgalm and whether the alarm condition still exists. 3 to 0 (lsb) unused readback bits loads with 0s.
ad5522 rev. d | page 57 of 64 readback of dac register the dac register readback function is a 24-bit word that includes the mode, address, and dac data bits. table 35. dac register readback bit bit name description 23 (msb) mode1 22 mode0 the mode1 and mode0 bits indicate the type of dac register (x1, m, or c) that is read. 01 = dac gain (m) register. 10 = dac offset (c) register. 11 = dac input data (x1) register. dac register-specific bits 21 to 16 a5 to a0 address bits indicating the dac register that is read (see table 29 ). 15 to 0 (lsb) d15 to d0 contents of the addressed dac register (x1, m, or c).
ad5522 rev. d | page 58 of 64 applications information power-on default the power-on default for all dac channels is that the contents of each m register are set to full scale (0xffff), and the contents of each c register are set to midscale (0x8000). the contents of the dac x1 registers at power-on are listed in table 36 . the power-on default for the alarm status register is 0xfffff0, and the power-on default for the comparator status register is 0x400000. the power-on default values of the pmu register and the system control register are shown in table 3 7 and table 38 . se tting up the device on power-on on power-on, default conditions are recalled from the power- on reset register to ensure that each pmu and dac channel is powered up in a known condition. to operate the device, the user must follow these steps: 1. configure the device by writing to the system control register to set up different functions as required. 2. calibrate the device to trim out errors, and load the required calibration values to the gain (m) and offset (c) registers. load codes to each dac input (x1) register. when x1 values are loaded to the individual dacs, the calibration engine calculates the appropriate x2 value and stores it, ready for the pmu address to call it. 3. load the required pmu channel with the required force mode, current range, and so on. loading the pmu channel configures the switches around the force amplifier, measure function, clamps, and comparators, and also acts as a load signal for the dacs, loading the dac register with the appropriate stored x2 value. 4. because the voltage and current ranges have individual dac registers associated with them, each pmu register mode of operation calls a particular x2 register. therefore, only updates (that is, changes to the x1 register) to dacs associated with the selected mode of operation are reflected in the output of the pmu. if there is a change to the x1 value associated with a different pmu mode of operation, this x1 value and its m and c coefficients are used to calculate a corresponding x2 value, which is stored in the correct x2 register, but this value is not loaded to the dac. table 36. default contents of dac registers at power-on dac register default value offset dac 0xa492 fin dac 0x8000 cll dac 0x0000 clh dac 0xffff cpl dac 0x0000 cph dac 0xffff table 37. power-on default for system control register bit bit name default value 21 (msb) cl3 0 20 cl2 0 19 cl1 0 18 cl0 0 17 cpolh3 0 16 cpolh2 0 15 cpolh1 0 14 cpolh0 0 13 cpbiasen 0 12 dutgnd/ch 0 11 guard alm 0 10 clamp alm 0 9 int10k 0 8 guard en 0 7 gain1 0 6 gain0 0 5 tmp enable 1 4 tmp1 0 3 tmp0 0 2 latched 0 1 unused data bit 0 0 (lsb) unused data bit 0 table 38. power-on default for pmu register bit bit name default value 21 (msb) ch en 0 20 force1 0 19 force0 0 18 reserved 0 17 c2 0 16 c1 1 15 c0 1 14 meas1 1 13 meas0 1 12 fin 0 11 sf0 0 10 ss0 0 9 cl 0 8 cpolh 0 7 compare v/i 0 6 ltmpalm 1 5 tmpalm 1 4 unused data bit 0 3 unused data bit 0 2 unused data bit 0 1 unused data bit 0 0 (lsb) unused data bit 0
ad5522 rev. d | page 59 of 64 changing modes th ere are different ways of handling a mode change. 1. load any dac x1 values that require changes. remember that for force amplifier and comparator dacs, x1 registers are available per voltage and current range, so the user can preload new dac values to make dac updates ahead of time; the calibration engine calculates the x2 values and stores them. 2. change to the new pmu mode (fi or fv). this action loads the new switch conditions to the pmu circuitry and loads the dac register with the stored x2 data. th e following steps describe another method for changing modes: 1. in the pmu register (bit 20 and bit 19), enable the high-z voltage or high-z current mode to make the amplifier high impedance (sw5 open). 2. load any dac x1 values that require changes. remember that for force amplifier and comparator dacs, x1 registers are available per voltage and current range, so the user can preload new dac values to make dac updates ahead of time; the calibration engine calculates the x2 values and stores them. 3. when the high-z (voltage or current) mode is used, the relevant dac outputs are automatically updated (fin, cll, and clh dacs). for example, in high-z voltage mode, when new x1 writes occur, the fin voltage x2 result is calculated, cached, and loaded to the fin dac. when forcing a voltage, current clamps are engaged, so the cll current register can be loaded, and the gain and offset corrected and loaded to the dac register. (the clh current register works the same way.) 4. change to the new pmu mode (fi or fv). this action loads the new switch conditions to the pmu circuitry. because the dac outputs are already loaded, transients are minimized when changing current or voltage mode. required external components the minimum required external components for use with the ad5522 are shown in figure 58 . decoupling is greatly dependent on the type of supplies used, other decoupling on the board, and the noise in the system. it is possible that more or less decoupling may be required. dutgnd dut extmeasih3 extmeasil3 foh3 extfoh3 ccomp[0:3] vref measvh3 cff3 ref a vdd avss dvcc avdd avss dvcc dut extmeasih2 extmeasil2 foh2 extfoh2 measvh2 cff2 dut extmeasih0 extmeasil0 foh0 extfoh0 measvh0 cff0 dut extmeasih1 extmeasil1 foh1 extfoh1 measvh1 cff1 10f 10f 10f 0.1f 0.1f 0.1f 0.1f 06197-037 r sense (up to 80ma) r sense (up to 80ma) r sense (up to 80ma) r sense (up to 80ma) figure 58. external components re quired for use with the ad5522
ad5522 rev. d | page 60 of 64 table 39. adcs and adc drivers suggested for use with ad5522 1 part no. resolution sample rate ch. no. ain range interface adc driver multiplexer 2 package ad7685 16 250 ksps 1 0 v to vref serial, spi ada4841-x adg704 , adg708 msop, lfcsp ad7686 16 500 ksps 1 0 v to vref serial, spi ada4841-x adg704 , adg708 msop, lfcsp ad7693 3 16 500 ksps 1 ?vref to +vref serial, spi ada4841-x , ada4941-1 adg1404 , adg1408 , adg1204 msop, lfcsp ad7610 16 250 ksps 1 bipolar 10 v, bipolar 5 v, unipolar 10 v, unipolar 5 v serial/parallel ad8021 adg1404 , adg1408 , adg1204 lfcsp, lqfp ad7655 16 1 msps 4 0 v to 5 v serial/parallel ada4841-x / ad8021 1 subset of the possible adcs su itable for use with the ad5522. visit www.analog.com for more options. 2 for purposes of sharing an adc among multiple pmu channels. note that the multiplexer is not absolutely necessary because the ad5522 measoutx path has a tri- state mode per channel. 3 do not allow the measoutx output range to exceed the analog input (ain) range of the adc. power supply decoupling careful consideration of the power supply and ground return layout helps to ensure the rated performance. design the printed circuit board (pcb) on which the ad5522 is mounted so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5522 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. establish the star ground point as close as possible to the device. for supplies with multiple pins (avss and avdd), it is recommended that these pins be tied together and that each supply be decoupled only once. the ad5522 should have ample supply decoupling of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capac- itors should have low effective series resistance (esr) and low effective series inductance (esl)typical of the common ceramic types that provide a low impedance path to ground at high frequenciesto handle transient currents due to internal logic switching. avoid running digital lines under the device because they can couple noise onto the device. however, allow the analog ground plane to run under the ad5522 to avoid noise coupling (applies only to the package with paddle up). the power supply lines of the ad5522 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the refer- ence inputs. it is essential to minimize noise on all vref lines. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. as is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. also, note that the exposed paddle of the ad5522 is connected to the negative supply, avss. power supply sequencing when the supplies are connected to the ad5522, it is important that the agnd and dgnd pins be connected to the relevant ground planes before the positive or negative supplies are applied. this is the only power sequencing requirement for this device. typical application for the ad5522 figure 59 shows the ad5522 used in an ate system. the device can be used as a per-pin parametric unit to speed up the rate at which testing can be done. the central pmu (shown in the block diagram) is usually a highly accurate pmu and is shared among a number of pins in the tester. in general, many discrete levels are required in an ate system for the pin drivers, comparators, clamps, and active loads. dac devices such as the ad537x family offer a highly integrated solution for a number of these levels.
ad5522 rev. d | page 61 of 64 dut 50 ? coax gnd sense 06197-038 ad5522 dac dac v term vh driver comp vth iol vcom ioh vtl adc relays dac dac dac adc dac dac dac vcl vl vch driven shield guard amp central pmu timing data memory timing generator dll, logic dac dac dac guard amp dac dac ad5560 device power supply adc formatter deskew formatter deskew compare memory dac active load dac dac pmu pmu pmu pmu figure 59. typical applications circuit using the ad5522 as a per-pin parametric unit
ad5522 rev. d | page 62 of 64 outline dimensions compliant to jedec standards ms-026-add-hd 0.27 0.22 0.17 1 20 21 40 40 61 80 60 41 14.20 14.00 sq 13.80 12.20 12.00 sq 11.80 0.50 bsc lead pitch 0.75 0.60 0.45 1.20 max 1 20 21 61 80 60 41 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 9.50 bsc sq bottom view (pins up) exposed pad for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 071808-a figure 60. 80-lead thin quad flat package, exposed pad [tqfp_ep] sv-80-3 dimensions shown in millimeters compliant to jedec standards ms-026-add-hu 071808-a 0.27 0.22 0.17 1 20 21 40 40 61 80 60 41 14.20 14.00 sq 13.80 12.20 12.00 sq 11.80 0.50 bsc lead pitch 0.75 0.60 0.45 1.20 max 1 20 21 61 80 60 41 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 6.50 bsc 9.50 bsc bottom view (pins up) exposed pad for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 61. 80-lead thin quad flat package, exposed pad [tqfp_ep] sv-80-2 dimensions shown in millimeters
ad5522 rev. d | page 63 of 64 ordering guide model 1 temperature range (t j ) package description package option ad5522jsvdz 25c to 90c 80-lead tqfp_ep with exposed pad on bottom sv-80-3 AD5522JSVUZ 25c to 90c 80-lead tqfp_ep with exposed pad on top sv-80-2 eval-ad5522ebdz evaluation board with exposed pad on bottom eval-ad5522ebuz evaluation board with exposed pad on top 1 z = rohs compliant part.
ad5522 rev. d | page 64 of 64 notes ?2008C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06197-0-2/11(d)

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